Transcript Flip Flops - Stmik Akakom

Digital Electronics
Flip-Flops
Objectives:
• Given input logice levels, state the output of an RS
NAND and RS NOR.
• Given a clock signal, determine the PGT and NGT.
• Define “Edge Triggered” and “Level Triggered”.
• Draw a Clocked F/F with and “Edge Triggered”
clock input and a “Level Triggered” clock input.
LOGIC CIRCUITS
Logic circuits are classified into two groups:
Combinational logic circuits
Logic gates make decisions
Basic building
blocks include:
Sequential logic circuits
Basic building blocks
include FLIP-FLOPS:
Flip Flops have memory
FLIP-FLOPS
•Memory device capable of storing one bit
S
R
Q
•Memory means circuit remains in one
state after condition that caused the state
is removed.
Q
•Two outputs designated Q and Q-Not that
are always opposite or complimentary.
•When referring to the state of a flip flop,
referring to the state of the Q output.
FLIP-FLOPS
Symbol
SET
RESET
S
Q
R
Q
Truth Table
S
0
1
0
1
R
0
0
1
1
MODE
Q
Invalid
RESET
Q=0
Q=1
SET
No change
•To SET a flip flop means to
make Q =1
•To RESET a flip flop means to
make Q = 0
FLIP-FLOPS
5V
+V
OUTPUT
Q
1k
NPN
1k
1k
1k
1k
1k
OUTPUT
NOT Q
NPN
1k
1k
set
input
reset
input
•The flip flop is a bi-stable multivibrator; it has two stable states.
•The RS flip flop can be implemented with transistors.
R-S FLIP-FLOP
Symbols:
Set
Normal
S
Q
FF
R
Reset
Q
Complementary
Truth Table:
Mode of Operation
Prohibited
Set
Reset
Hold
Inputs
S R
0
0
1
1
NOTE: Active-LOW inputs
0
1
0
1
Outputs
Q Q’
1
1
0
Q
1
0
1
Q’
R-S FLIP-FLOP
Active-Low
NAND LATCH
Q
SET
7400
Q NOT
RESET
7400
DEMORGANIZED NAND LATCH
NAND LATCH
Q
SET
Q NOT
RESET
SET
0
0
1
1
RES Q NOT-Q MODE
0 1 1 PROHIBITED
1 1 0 SET
0 0 1 RESET
1 NO CHG HOLD
ACTIVE-LOW R-S FLIP-FLOP
TIMING DIAGRAMS
S
Q
R
R
Q
S
Q
S
0
0
1
1
R
0
1
0
1
MODE
Q
R
Invalid
Q=1
SET
Q=0
RESETS
No change
Q
R
S
Q
R
S
Q
R-S FLIP-FLOP
Active-High
SET
R Latch
Q
Normally
low
Q
RESET
Q
ET
SET
Q
Q
S
Q
R
QS
Q
R
Q
Q
S
S
00
110
01
1
R
0
0
1
1
S
Q
R
Q
R
Q
Q
0No change
No chang
Q=1
0 Q=1
Q=0
1 Invalid Q=0
1
Invalid
ACTIVE-HIGH R-S FLIP-FLOP
Q
Q
Q
Q
S
Q
R
Q
S
0
1
0
1
TIMING DIAGRAMS
R
Q
0
No change
Q=1
0R
1
Q=0
S
1
Invalid
Q
S
0
1
0
1
R
0
0
1
1
Q
No change
Q=1
Q=0
Invalid
R
S
Q
R
S
Q
R
S
Q
TEST
Memory
1. Logic gates make decisions, flip flops have ____________________?
2. One flip flop can store how many bits?
1
3. What are the two outputs of a flip flop?
Q
Q-NOT
4. When referring to the state of a flip flop, we’re referring to the state
of which output?
Q
5. What does it mean to SET a flip flop?
6. What does it mean to RESET a flip flop?
Q=1
Q=0
TEST
What is the mode of operation of the R-S flip-flop (set, reset or hold)?
What is the output at Q from the R-S flip-flop (active LOW inputs)?
L
H
H
H
H
L
?High
Mode of operation =
Set
?
?High
Mode of operation =
Hold
?
? Low
Mode of operation =
?
Reset
CLOCKED R-S FLIP-FLOP
Set
S
Set
FF
S
Q
FF
Q
Clock
CLK
Reset
R
Q
ASYNCHRONOUS
Outputs of logic circuit can
change state anytime one or
more input changes
Reset
R
Q
SYNCHRONOUS
Clock signal determines exact
time at which any output can
change state
Clock
Digital signal in the form of a rectangular
or square wave
Astable
multivibrator
A clocked flip flop changes state only when
permitted by the clock signal
TRIGGERING OF FLIP-FLOPS
• Level-triggering is the transfer of data from input to
output of a flip-flop anytime the clock pulse is proper
voltage level.
• Edge-triggering is the transfer of data from input to
output of a flip-flop on the rising edge (L-to-H) or falling
edge (H-to-L) of the clock pulse. Edge triggering may be
either positive-edge (L-to-H) or negative-edge (H-to-L).
PGT-Positive Going Transition
Positive-edge triggering
NGT-Negative Going Transition
Negative-edge triggering
H
time
L
Level triggering
CLOCKED R-S FLIP-FLOP
Symbols:
Set
S
FF
Normal
Q
Clock
CLK
Reset
R
Q
Complementary
Truth Table:
Mode of operation
Hold
Reset
Set
Prohibited
Clk
+ pulse
+ pulse
+ pulse
NOTE: Active-High inputs
Inputs
S R
0
0
1
1
0
1
0
1
Outputs
Q Q’
no change
0 1
1 0
0 0
TEST
What is the mode of operation of the clocked R-S flip-flop (set, reset, hold)?
What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)?
H
^
L
L
?High
Mode of operation = ? Set
?High
^
L
L
^
H
Mode of operation = ?Hold
?Low
Mode of operation = ?Reset
CLOCKED R-S FLIP-FLOP
TIMING DIAGRAMS
Q
Q
C
0
1
1
1
1
S
Q
C
R
Q
R
X
0
0
1
1
S
X
0
1
0
1
S
0
1
0
1
R
0
0C
1R
1
S
Q
No change
Q=1
Q=0
Invalid
Q
Q
No change
No change
1
0
Illegal
C
R
S
Q
Q
Q
S
Q
C
R
Q
S
0
1
0
1
R
0C
0R
1
1S
Q
Q
No change
Q=1
Q=0
Invalid
POSITIVE EDGE TRIGGERED
Symbols:
R-S FLIP-FLOP
EDGE TRIGGERED R-S FLIP FLOP
Q
SET
CLOCK
Q NOT
RESET
CLK SET
PGT 0
PGT 0
PGT 1
PGT 1
Truth Table:
RES Q NOT-Q MODE
0 NO CHG HOLD
1 0 1
RESET
0 1 0
SET
1 1 1
INVALID
CLK
R
S
Q
0
1
X
X
X
X
NO CHG
NO CHG
X
X
NO CHG
0
0
0
1
1
1
0
1
NO CHG
SET
RESET
ILLEGAL
S
CLK
Q
R
Q
POSITIVE EDGE TRIGGERED
R-S FLIP-FLOP
TIMING DIAGRAMS
S
CLK
Q
R
Q
C
R
CLK
R
S
0
0
0
1
1
1
0
1
Q
NO CHG
SET
RESET
ILLEGAL
S
Q
NEGATIVE EDGE TRIGGERED
Symbols:
R-S FLIP-FLOP
EDGE TRIGGERED R-S FLIP FLOP
Q
SET
CLOCK
EDGE
DETECTOR
Q NOT
RESET
CLK SET
PGT 0
PGT 0
PGT 1
PGT 1
Truth Table:
RES Q NOT-Q MODE
0 NO CHG HOLD
1 0 1
RESET
0 1 0
SET
1 1 1
INVALID
CLK
R
S
Q
0
1
X
X
X
X
NO CHG
NO CHG
X
X
NO CHG
0
0
0
1
1
1
0
1
NO CHG
SET
RESET
ILLEGAL
S
CLK
Q
R
Q
NEGATIVE EDGE TRIGGERED
R-S FLIP-FLOP
TIMING DIAGRAMS
S
CLK
Q
R
Q
C
R
CLK
R
S
0
0
0
1
1
1
0
1
Q
NO CHG
SET
RESET
ILLEGAL
S
Q
TEST
1. Type of flip flop where the outputs of circuit can change state anytime
one or more input changes?
ASYNCHRONOUS
2. Type of flip flop where the clock signal controls when any output can
change state?
SYNCHRONOUS
3. What do we call a digital signal in the form of a repetitive pulse or square wave?
CLOCK
4. Which is easier to design and troubleshoot, clocked or not clocked flip flops?
Clocked flip flops are easier to troubleshoot because we can
stop the clock and examine one set of input and output
conditions.