Transcript Slide 1
ECM583 Special Topics in Computer Systems
Lecture 1. General-Purpose Computer Systems
Prof. Taeweon Suh Computer Science Education Korea University
A Computer System (till 2008)
Peripheral devices CPU FSB (Front-Side Bus) Graphics card North Bridge DMI (Direct Media I/F) Hard disk USB PCIe card But, don’t forget the big picture!
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Main Memory (DDR2) South Bridge Korea Univ
Present, Near Future and More…
•
Core 2 Duo – based Systems
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Core i7– based Systems CPU FSB (Front-Side Bus) North Bridge Main Memory (DDR2) DMI (Direct Media I/F) South Bridge Quickpath (Intel) or Hypertransport (AMD) CPU North Bridge DMI (Direct Media I/F) Main Memory (DDR3) South Bridge Keep in mind that CPU and computer systems are evolving at a fast pace
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x86 History (as of 2008)
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x86 History (Cont.)
4-bit 8-bit 16-bit 32-bit (i386) 32-bit (i586) 32-bit (i686)
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64-bit (x86_64) 2009 Core i7 Korea Univ
x86?
• What is x86?
Generic term referring to processors from Intel, AMD and VIA Derived from the model numbers of the first few generations of processors: • 80
86
, 802
86
, 803
86
, 804
86
x86
Now it generally refers to processors from Intel, AMD, and VIA • x86-16: 16-bit processor • • x86-32 (aka IA32): 32-bit processor * IA: Intel Architecture x86-64: 64-bit processor • Intel takes about 80% of the PC market and AMD takes about 20% Apple also have been introducing Intel-based Mac from Nov. 2006 6
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Example: Intel’s Core 2 Duo
L1 L2 32 KB , 8-Way, 64 Byte/Line, LRU, WB 3 Cycle Latency 4.0 MB , 16-Way, 64 Byte/Line, LRU, WB 14 Cycle Latency
Core0 DL1 DL1 IL1 Core1 IL1 L2 Cache
Source: http://www.sandpile.org
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Example: Intel’s Core i7
• • • 4 cores on one chip Three levels of caches (L1, L2, L3) on chip • L1 :
32KB
, 8-way • L2 :
256KB
, 8-way • L3 :
8MB
, 16-way 731 million transistors in 263 mm 2 with 45nm technology 8
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Example: AMD’s Opteron - Barcelona
• • • • • 4 cores on one chip 1.9GHz clock 65nm technology Three levels of caches (L1, L2, L3) on chip •
L1: 64KB, L2: 512KB, L3: 2MB
Integrated North Bridge 9
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Chipset
• We call North and South Bridges as Chipset • Chipset has many PCIe devices inside • • North Bridge Memory controller PCI express ports to connect Graphics card http://www.intel.com/Assets/PDF/datasheet/316966.pdf
South Bridge HDD (Hard-disk) controller USB controller Various peripherals connected • Keyboard, mouse, timer etc PCI express ports http://www.intel.com/Assets/PDF/datasheet/316972.pdf
• Note that the landscape is being changed! For example, memory controller is integrated into CPU 10
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PCI, PCI Express Devices
• PCI (Peripheral Component Interconnect) Computer bus connecting all the peripheral devices to the computer motherboard • PCIe (PCI Express) Replaced PCI in 2004 Point-to-point connection
PCI slot PCI express slots PCI express slot x16
http://www.pcisig.com/specifications/pciexpress/ 11
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An Old GP Computer System Example
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PCI Express Slots in GP Systems
PCI express slot
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GP Computer System in terms of PCIe
North Bridge South Bridge
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Core i7-based Systems
• Core i7 860 (Lynnfield) – based system • Core i7 920 (Bloomfield) – based system 15
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Hardware/Software Stack in Computer
Applications (MS-office, Google Earth…)
API (Application Program I/F)
Operating System (Linux, Vista, Mac OS …)
BIOS provides common I/Fs
BIOS (AMI, Phoenix Technologies …) Instruction Set Architecture (ISA) Computer Hardware (CPU, Chipset, PCIe cards ...)
• Application software Written in high-level language • System software Compiler • Translates
code written in high-level language
to
machine code
Operating System • Handling input/output • • Managing memory and storage Scheduling tasks & sharing resources BIOS (Basic Input/Output System) • ISA Interface between hardware and low-level software • Hardware Processor, memory, I/O controllers 16
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How the GP Computer System Works?
• x86-based system starts to execute from the
reset address 0xFFFF_FFF0
The first instruction is “
jmp xxx
” off from BIOS ROM • BIOS (Basic Input/Output System) Detect and initialize all the devices (including PCI devices via PCI enumeration) on the system Provide common interfaces to OS Hand over the control to OS • OS Manage the system resources including main memory • Control and coordinate the use of the hardware among various application programs for the various users Provide APIs for system and application programming 17
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GP Systems’ Differences from Other Computer Systems
• How is it different from other computers systems such as embedded systems?
General-purpose computer systems provide
programmability
to end-users • You can do any kinds of programming on your PC C, C++, C#, Java etc General-purpose systems should provide
compatibility
•
backward
A new system should be able to run legacy software, which could be in the form of binaries with no source codes written 30 years ago So, general purpose computer system becomes messy and complicated, still containing all legacy hardware functionalities 18
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Abstraction
• Abstraction helps us deal with complexity
Hide lower-level detail
• Instruction set architecture (ISA)
An abstract interface between the hardware and the low-level software interface 19
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Abstraction Analogies
Driver Customer Abstraction layer Abstraction layer Machine Details Combustion Engine in a car Break system in a car
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Machine Details Hardware board in a vending machine Korea Univ
Users Abstraction layer Abstraction layer Hardware implementation
Abstraction in Computer
Application programming using APIs Operating Systems Instruction Set Architecture (ISA) Provides APIs (Application Programming Interface) Machine language Assembly language Core0 Core1 L2 Cache
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A Typical Memory Hierarchy
• Take advantage of the
principle of locality
to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology
higher level lower level
CPU Core
Reg File
On-Chip Components
L1I (Instr Cache) L1D (Data Cache) L2 (Second Level) Cache Main Memory (DRAM) Secondary Storage (Disk) Speed (cycles)
: ½’s 1’s 10’s 100’s 10,000’s
Size (bytes) :
100’s 10K’s M’s G’s T’s
Cost
: highest lowest 22
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Typical and Essential Instructions
• Instruction categories
Arithmetic and Logical (Integer)
Memory Access Instructions
• Load and Store
Branch Floating Point Registers in x86 EAX, EBX, ECX, EDX ..
CS, DS, SS, ES…
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Levels of Program Code
• High-level language Level of abstraction closer to problem domain Provides for productivity and portability • Assembly language Textual and symbolic representation of instructions • Hardware representation Binary digits (bits) Encoded instructions and data 24
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Instructions and Instruction Set
• If you want to talk to foreigners, you should be able to speak their languages Likewise, to talk to a computer, you must speak its language • The words of a computer’s language are called
instructions
• The collection of instructions is called
instruction set
• Different CPUs have different instruction sets x86 has its own instruction set ARM has its own instruction set But, they have many aspects in common 25
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x86 Instruction Examples
• For more information on the complete instruction sets of x86, refer to the following links http://www.intel.com/products/p rocessor/manuals/ 26
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High Level Code to Assembly to Executable
• What steps do you take to run your program after writing your code “hello.c” on your Linux machine?
#include
// hello is a machine code (binary or executable)
%objdump –D hello // it shows human-readable code 27
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Reality check: High Level Code to Assembly to Executable
C program
preprocessor cpp
(C-preprocessor) in Linux GNU C Expanded C program
compiler gcc
in Linux GNU C
assembly code assembler as
in Linux GNU
Human-readable assembly code Machine code object code linker library routines ld
in Linux GNU
Linux kernel
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executable
loads the executable into memory
loader
memory
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Reality check: High Level Code to Assembly to Executable (Cont)
• The command “gcc” hides all the details • Try to compile hello.c with “gcc –v hello.c –o hello” You will see all the details of what gcc does for compilation • Compilation goes through several steps to generate machine code #include
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Reality check: High Level Code to Assembly to Executable (Cont)
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Preprocessing
Use to expand macros and header files included %
cpp
hello.c > hello.i
• open “hello.i” to see what you got •
Compilation
Actual compilation of the preprocessed code to assembly language
for a specific processor %
gcc
-Wall -S hello.i
• • Result will be stored in hello.s
Open hello.s to see what you got •
Assembler
Convert
assembly language
into
machine code
and generate an object file %
as
• hello.s -o hello.o
The resulting file ‘hello.o’ contains the machine instructions for the World program, with an undefined reference to printf Hello 30
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Reality check: High Level Code to Assembly to Executable (Cont)
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Linker
Final stage of compilation Linking object files to create an executable In practice, an executable requires many external functions from system and C run-time (crt) libraries Consequently, the actual link commands used internally by GCC are complicated.
Example • %
ld
-dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o /usr/lib/crti.o
/usr/lib/gcc/i386-redhat-linux/4.3.0/crtbegin.o -L/usr/lib/gcc/i386 redhat-linux/4.3.0
hello.o
-lgcc -lgcc_eh -lc -lgcc -lgcc_eh /usr/lib/gcc/i386-redhat-linux/4.3.0/crtend.o /usr/lib/crtn.o -o
hello
• Note that “i386-redhat-linux/4.3.0/” is dependent on your Linux version •
Now run your program
%./hello //
Linux kernel loads the program into memory
%Hello World! // output 31
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Stored Program Concept
CPU FSB (Front-Side Bus) North Bridge DMI (Direct Media I/F) Main Memory (DDR) South Bridge CPU Memory (DDR)
Hello World Binary (machine code)
Address Bus 11100111 00110000 01010101 11000011 10100000 00011111 11100111 00011110 11110011 11000011 00110011 01010101 Data Bus
C compiler (machine code) • • • • •
Instructions are represented in binary, just like data Instructions and data are stored in memory CPU fetches instructions and data to execute
Programs can operate on programs e.g., compilers, linkers, … Binary compatibility allows compiled programs to work on Standardized ISAs 32 “Hello World” Source code in C
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CPU Operation
Registers 32 bits CPU (MIPS) $zero $at $v0 … $fp $ra PC
R3
Address Bus Memory Data Bus 0x0018 0x0014 0x0008 0x0004 0x0000
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