A Novel, Highly SEU Tolerant Digital Circuit Design Approach

By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX 1

Outline



Background and Motivation



Previous Work



Our Approach



Experimental Results



Conclusions

2

Charge Deposition by a Radiation Particle

     Radiation particles - protons, neutrons, alpha particles and heavy ions Reverse biased

p-n

junctions are most sensitive to particle strikes Charge is collected at the drain node through

and diffusion drift

Radiation Particle VDD

Results in a voltage glitch at the drain node

S G

System state may change if this voltage glitch is captured by at least one memory element   This is called SEU May cause system failure

n + p-substrate

+ + _ _ _ _ + _ + + + + + E

n +

E

D

Depletion Region VDD - V jn

B

3

Modeling a Radiation Particle Strike

   Charge deposited (

Q

) at a node is given by

Q

 0 .

01036 

L



t

where:

L

is the Linear Energy Transfer (

MeV-cm 2 /mg

)

t

is the depth of the collection volume (

mm

) A radiation particle strike is modeled by a current pulse as

i seu

(

t

)

where

: t a t b  t a

Q

 t b (

e



t

/ t a 

e



t

/ t b is the collection time constant is the ion track establishment constant ) The radiation induced current always flows from

n

diffusion to

p

-diffusion 4

Motivation



Modern VLSI Designs

 Vulnerable to noise effects- crosstalk, SEU, etc  Single Event Upsets

(SEUs) or Soft Errors

 Troublesome for both memories and combinational logic  Becoming increasingly problematic even for terrestrial designs 

Applications demand reliable systems

 Need to efficiently design radiation tolerant circuits  This is the focus of this talk 5

Previous Approaches for Radiation Hardening

      Gate sizing is done to improve the radiation tolerance of a design (Zhou et al.)   Higher drive capability and higher node capacitance increase immunity to SEU Selectively harden gates in a circuit to reduce SER by 10X SEU events are detected using built in current sensors (BICS) (Gill et al.) Error correction codes (Gambles et al.) Triple modulo redundancy based approaches (Neumann et. al) SOI devices are inherently less susceptible  to radiation strikes Still needs other hardening techniques to achieve SEU tolerance Several other approaches exist to reduce the severity of radiation particle strikes (Heijmen et al., Mohanram et al. ) 6

Our Approach

 Phase 1  Gate level hardening  Phase 2  Block level hardening  Selectively harden critical gates in a circuit  To keep area and delay overheads low  Reduce SER by 10X 7

in

Gate Level Hardening Approach

 A radiation particle strike at a reverse biased p-n junction results in a current flow from n-type diffusion to p-type diffusion  A gate constructed using only PMOS (NMOS) transistors cannot experience 1 to 0 (0 to 1) upset Radiation Particle

inp out1p out1 out2 inp & inn out2 out1n

VDD - V TN |V TP | INV1 INV2 Radiation Particle

inn

INV1

out1n

INV2

out1p out2 Static Leakage Paths

8

inp inn out1p

Our Gate Level Hardening Approach

Low V T transistors

inp out1p inp & inn

VDD - V TN

X

out2 out2 out1n

|V TP |

out1p out1n

X

out2 out1n

Radiation Tolerant Inverter

inn

Leakage currents are lower by ~100X Modified Inverter 9

Radiation Tolerant Inverter

inp

M2

X X X

out1p

M4 M6

X

M8

out2 inp & inn out1n out1p

X

M5 M3

out2 inn out1n

M1

X

M7

Radiation Particle Strike The voltage at Radiation Particle Strike

first inverter (radiation tolerant inverter) does not affect the voltage at out2

10

Radiation Tolerant Inverter

inp

 Radiation particle strike at the outputs of INV1   Implemented using 65nm PTM with VDD=1V Radiation strike:

Q

=150fC, t a =150ps & t b =38ps

out1p out2 inn

INV1

out1n

11

Block Level Radiation Hardening

  100% SEU tolerance can be achieved by hardening all gates in a circuit but this will be very costly Protect only sensitive gates in a circuit to achieve good SEU tolerance or coverage    We obtain these sensitive gates using

Logical Masking P LM (G)

is the probability that the voltage glitch due to a radiation particle strike gets logically masked

P Sen (G)

= 1 –

P LM (G)

For all inputs P 1 = 0.5 P 0 = 0.5

1 0 1 2 1 0 0 P 1 = 0.25 P 0 = 0.75

→ 1 = 0.5 3 1 Gate

1 2 3

P LM

0.5

0.75

0

P Sen

0.5

0.25

1 

If we want to protect only 2 gates then we should to protect Gates 1 and 3 to maximize SEU tolerance

 Gate 3 is the most sensitive 12

Block Level Radiation Hardening

     Obtained

P Sen

for all gates in a circuit using a fault simulator Sort these gates in decreasing order of their

P Sen

Harden gates until the required

coverage



Coverage



All

_

G P Sen

_

G

 

All

_

hardened



gates

_

G P Sen G

  *  100 is achieved  Coverage is a good estimate for SER reduction (Zhou et al.) Gates at the primary output of a circuit need to be hardened since

P Sen

= 1 for these gates The dual outputs of the hardened gates at the primary outputs drive the dual inputs of an SEU tolerant flip-flip (such as the flip-flop proposed by Liu et al.) 13

Critical Charge (Q

cri

)

   Minimum amount of charge which can result in an SEU event Our hardened gates can tolerate a large amount of charge dumped by a radiation particle  Operating frequency of circuit determines

Qcri

CLK in out1n out1p

Q cri

is the amount of charge which results in a voltage glitch of pulse width

T

out2 t 1 T + t 1 2T + t 1

14

Experimental Results

 We implemented a standard cell library

L

using a 65nm PTM model card with VDD = 1.0V

 Implemented both regular and hardened versions of all cell types  Applied our approach to several ISCAS and MCNC benchmark circuits  We implemented   A tool in

SIS

to find the sensitive gates in a circuit An STA tool to evaluate the delay of a hardened circuit obtained using our approach  Layouts were created for all gates in our library for both regular and hardened versions 15

Experimental Results

 Average results over several benchmark circuits mapped for area and delay optimality Avg. Results Area Mapped Delay Mapped Coverage 90% 100% 90% 100% % Area Ovh 62.4

97.7

58.15

96.5

% Delay Ovh 28.9

44.3

27.9

47.6

  Our SEU immune gates can tolerate high energy radiation particle strikes Critical charge is extremely high (>520fC) benchmark circuits  for all Suitable for space and military application because of the presence of large number of high energy radiation particles 16

Comparison Our Hardening Approach

 Our approach is suitable for radiation environments with high energy particles

90% Coverage Area Ovh.

Delay Ovh.

Critical Charge Zhou et al.

90% 8% ~150fC

Our Approach

58% 28% >520fC 17

Conclusions

 SEUs are troublesome for both memories and combinational logic  Becoming increasingly problematic even for terrestrial designs  Applications demand reliable systems  Need to efficiently design radiation tolerant circuits  We developed a circuit hardening approach  Area overhead is ~60%  Delay overhead is ~28%  Our approach is suitable for high energy radiation particle environments  Critical charge is >520fC 18

THANK YOU

19