Transcript IBM Presentations: Blue Pearl DeLuxe template

Thomas J. Watson Research Center
Statistical Timing in a Practical
65 nm Robust Design Flow
Chandu Visweswariah
© 2006 IBM Corporation
Thomas J. Watson Research Center
The power of statistical formulas
2 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Acknowledgements
 The extended statistical timing, statistical optimization,
timing support and timing methodology teams at IBM
Yorktown, Fishkill, Burlington, Poughkeepsie,
Rochester and Waltham
Caveat
 This presentation is mostly ASIC-focused, although
microprocessor design issues will be mentioned
(time permitting)
3 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Outline
 Yield loss mechanisms and the tradeoffs involved
 What is robust design?
 A timing closure methodology based on statistical
timing
 Myths about statistical timing
 Interesting challenges
– early/late splits and CPPR
– at-speed test
– metrics for optimization
– delay modeling for 45 nm
– hierarchical statistical timing
4 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Catastrophic vs. parametric yield loss
Dummy fill
Dummy fill
100%
Yield
80%
Defect Based
Lithography Based
60%
Parametric (design-based)
40%
20%
0%
Source: NEC
350nm
5 of 27
250nm
Statistical Timing in a Practical 65 nm Robust Design Flow
180nm
C2S2 Workshop
130nm
90nm
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Increasing and inevitable parametric variability
Litho-induced variability
Oxide thickness
Random dopant effects*
Interconnect CMP and RIE effects
*D. J. Frank et al, Symp. VLSI Tech., 1999
6 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Normalized metal resistance data over 3 months
3.0
We would like to
retain these wafers
2.5
2.0
1.5
1.0
 Wafer means change over time
 Values are “out-of-spec,” need to yield within WAC limit
7 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Manufacturing for predictable performance
Lower spec. limit
Nominal spec. Upper spec. limit
 Cp and Cpk (Process Capability Indices) measure manufacturing
predictability
 Manufacturing typically (but not always) outperforms spec. limits
8 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Normalized cumulative statistics
1.0
1.5
2.0
2.5
 Distributions are not Gaussian (but usually close)
9 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
spec
Slower
Ring oscillator performance distribution
Percentage of chips
 Color coding is by wafer
 Hardware is faster/tighter than predictions
10 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Normalized metal resistance across manufacturing lines
0.368 0.448 0.528 0.608 0.688 0.768 0.848 0.928
0.44
0.52
0.60
0.68
0.76
0.84
0.92
1.0
 Designs must yield at multiple fabs.
11 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Normalized single-level capacitance distribution
250
200
150
100
50
More
1.688
1.635
1.582
1.529
1.476
1.423
1.371
1.318
1.265
1.211
1.158
1.105
1.053
1.0
0
 Variability is enormous!
12 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Any performance left in worst-case design?
90 nm
65 nm
45 nm
13 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
What do we do with all this variability?
As we know,
There are known knowns.
There are things we know we know.
We also know
There are known unknowns.
That is to say
We know there are some things
We do not know.
Known
knowns
But there are also unknown unknowns,
The ones we don't know
We don't know.
Donald H. Rumsfeld1
1Dept.
14 of 27
Known Unknown
unknowns unknowns
Statistical
timing and
power analysis
of Defense news briefing, 2/12/02, linebreaks mine
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Robust circuit design
First order model
P( x, y )  m ean
p
 p 2
 x  2 x  
x
x
2
p
 p 2
 y  2 y  
y
y
2
 Its the sensitivities, stupid!
15 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Fast chip vs. slow chip
Delay modeling
Can get acrossparameter RSS relief
Can get spacedependent relief
Chip means
Systematic
ACV
Can get down-apath RSS relief
Early
16 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
Random
ACV
Late
C2S2 Workshop
Early
Late
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
RO delay
Early
Late
Model-to-hardware correlation
Fast chip
17 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
Mean RO delay
C2S2 Workshop
Slow chip
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Bounding distributions
1.0
1.5
2.0
2.5
 Bounding distributions provide protection from various sins!
18 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Statistical-timing-based flow
 Conduct statistical timing with correlations
– predict timing slacks in “canonical” form parameterized by the sources of variation
 “Project” flop slacks to worst corner; if positive, we are safe
 Get “debits” and “credits”
–
–
–
–
mixed-mode projection
spatial
coupling noise
independently random
 Check sensitivities
– alternative statement of Murphy’s law: “Variability exacerbates poor design!”
– encourage “balanced” or “robust” design
 Check single-corner timing with all bells and whistles
 Optimization and fix-up
– use incremental statistical timing
– various diagnostics available
19 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Myths about statistical timing
 “The main reason for statistical timing is withindie variations” … “Variability is dominated by
within-die variations” … “The main frequency
limiter is within-die variations”
 Random dopants are the only truly statistical
phenomena
 “Statistical timing is a good idea so long as you
don't assume that variations are statistical,” said
TI's (Dennis) Buss. About the only thing that's
truly statistical, he said, are random dopant
fluctuations.” (From EE Times article 7/26/06 by
Richard Goering)
20 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Courtesy Anne Gattiker, IBM
21 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Across-wafer variations
Courtesy Anne Gattiker, IBM
22 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Interesting challenges: early/late splits and CPPR
Undue pessimism
early clock
LL1
23 of 27
LL3
LL2
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
CL
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Interesting challenges: at-speed testing
From tester:
RefClk
Chip Under Test
PLL
StartTest
Clock control
Logic
Clk
Scan & Test Clocks
Test Data
PLL Output
Clk
Scan Clock
Last Scan-Load Cycle
At-Speed Test
Scan Unload Cycles
[Courtesy Gary Grise]
24 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Interesting challenges: at-speed testing
Critical
Critical
 Each point in the process space can have a unique critical path
 How to come up with a set of test vectors that tests
for parametric variations in all parts of the process space?
 How to measure coverage thereof?
 How to test against workload-related defects?
 How to test against fatigue-related defects?
25 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Interesting challenges: metrics for optimization
 Slack is lacking
– different critical paths in different parts of the process space
– slack is a distribution
– slack does not give robustness information
– relative ordering of paths
• slack does not give correlation information
Other open problems
 Delay+power+noise variational modeling for 45 nm
 Robust optimization, fix-up
 Hierarchical robust design
26 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission
Thomas J. Watson Research Center
Conclusions
 Must protect against parametric variability
– high dimensionality, hence the need for statistical timing
– hence the need for robust design
– hence the need to check sensitivities
– hence the need for statistical timing!
 IBM has adopted a statistical-timing-based robust
design flow for 65 nm ASICs
 Many open and interesting challenges remain
27 of 27
Statistical Timing in a Practical 65 nm Robust Design Flow
C2S2 Workshop
© 2006 IBM Corporation, do not copy without permission