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Fabrication Process
Lithography

Resist coating + soft bake

Exposure

Post-exposure bake + development
Etching

Silicon etch

Oxide Etch
Post processing

Dicing

Substrate thinning

Cleaving
© intec 2002
http://www.intec.rug.ac.be/groupsites/opto
Step 1: Bare SOI wafer
Layer structure

205 Top Si layer

400nm Buried Oxide
Wafer size

8” (200mm)
205nm
Si
400nm
SiO2
Si-substrate
© intec 2002
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Step 2: Photoresist Coating
Resist

Shipley UV3

800nm thick
Photoresist
© intec 2002
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Step 3: Soft baking of resist
Photoresist
© intec 2002
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Step 4: Antireflective coating
AR coating


No standing waves in resist
during lithography
AR-coating
40nm of NFC
© intec 2002
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Step 5: Illumination
Deep UV Lithography

Wavelength = 248nm

NA = 0.63

Dose = 10-40 mJ

Reduction = 4X
© intec 2002
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Step 6: Post-exposure bake
© intec 2002
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Step 7: Development
© intec 2002
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Step 8: Silicon etch
Etch properties

TCP9400PTX

ICP-RIE

Low pressure /high density

Cl2/HBr/He/O2 chemistry

Two-step

break-through

main etch
© intec 2002
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Step 9: Oxide Etch
Etch properties


Exelan

Dual frequency

Medium pressure /medium density
CF4/CHF3 chemistry
© intec 2002
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Step 10: Resist strip
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Step 11: Protective Resist Layer
Substrate thinning = dangerous
1-3m resist cover
Wafer is diced into
3 x 3 cm2 dies for
substrate thinning
© intec 2002
750m
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Step 12: Glue on glass plate
Glue = Bee’s wax

Heated to ± 130°C
Bee’s wax
Glass plate
© intec 2002
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Step 13: Substrate thinning
Mechanical grinding

Alumina powder

5-8 hours

Remove 500m
250m
Bee’s wax
Glass plate
© intec 2002
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Step 14: Cleaning and Cleaving
© intec 2002
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