Transcript Slide 1

MOSFET Device Simulation
MOSFET Device Structure
Semiconductor Equations
Poisson Equation:

q
     n  p  N D  N A

2

n
   J n  q R  G 
t
Electron current
continuity equation:
q
Hole current
continuity equation:
q
Electron current
equation:
J n  qnn  q(nDn )
Hole current
equation:
J p  qp p   q( pD p )
p
   J p  q R  G 
t
Simulation Methodology
Set up the device
dimensions, material
properties,
temperature, bias
voltages, doping
profile, etc.
Discretization of the
semiconductor
equations
Newton’s Method
for better
accuracy
Y
Converged?
N
Iterative Gummel
Block Method.
Solve for , n, p
Initial
Guess for
, n and p
N
Current
Continuity?
Y
Extract , electron and
hole concentrations,
mobility, current density,
IV characteristics, etc.
Mobility Models
Oxide
Low field mobility:
Matthiessen's rule
1
 LF

1
B

1
 SP

1
 SR

1
Electron Flow
C
LF = Low Field Mobility B = Bulk Mobility
Bulk
SP = Surface Phonon Mobility
Electron
Surface Phonon
SR = Surface Roughness mobility
Trap
Surface Roughness
C = Trapped interface charge mobility
High Field Mobility:
High field mobility:
 HF 
Fixed Charge
 LF
1
   LF E||   
 
1  
  vsat  
Caughey – Thomas Model for bulk mobility:
n 
 300

T


 D
1 
N
 ref
n  
0
T
n
n
  nmin




n
1


 
n
Temperature dependence:
T 
  nmin
Doping dependence:
1
n   
D
n
Surface Phonon Mobility:
 SP
1
 SP

q ac

mc
 n E
 n 
2
1     E 3
T 
ac = Surface acoustic phonon relaxation time
E┴ = Perpendicular E. Field
n, n = calculated from phonon scattering
equation
Surface Roughness Mobility:
1
 SR

SR = Surface roughness parameter.
E2
 SR
Higher the value of SR, smoother is the surface and
lesser is the degradation in total mobility
Interface Trap Charge Mobility:
Corresponds to effect of coulomb scattering of mobile charged carriers
by fixed charge and interface trap charge. The term also accounts for
the screening of these charges by electrons at strong inversion.
1
C

nf  Nit
Temp
 T 


300




ne

 1 
screen_fit


screen_factor
 it
nf = Fixed oxide charge
Nit = Occupied interface trap density
ne = Inversion layer electron concentration
temp = Temperature dependence
screen_fit, screen_factor = fitting parameters
for the screening effect
it = from Coulomb Scattering
model
4H SiC 200m x 200m MOSFET:
Id-Vgs Simulation Fit at T=27oC
4H SiC 200m x 200m MOSFET:
Id-Vds Simulation Fit at T=27oC
Bulk Mobility ….
n 
 300

 T 
 D
1 
N
 ref
n  
0
T
n
  nmin




n
  nmin
Parameter
6H SiC
4H SiC
n0 in cm2/Vs
500.0
1071.0
nmin in cm2/Vs
0.0
5.0
Bulk mobility at
Room Temperature
and D ~ 1015 is
n
2.4
2.5
4H SiC: ~ 800 cm2/Vs
Nref
1.1e18
1.9e17
n
0.45
0.40
6H SiC: ~ 400 cm2/Vs
Surface Phonon Mobility ….
1
 SP

 n E
 n 
3

 n   bulk  ac 
2

2
1     E 3
T 
1
h3vs2
 ac  2 *
8 m mc Z A2

2 q  9h
n 


3 k B  16 2 qm 
2
1
3
Units
6H
4H
m1, m2, m3
-
0.22, 0.90, 1.43
0.29, 0.58, 0.33
m┴
-
0.44
0.41
m║
-
1.43
0.33
mc
-
0.35
0.39
m*
-
0.44
0.41
ZA
eV
17.5
15.0
bulk
gm/cm3
3.2
3.2
n
(cm/s)-1
2.99e-9
2.29e-9
n
(V/cm)-2/3K
0.1217
0.1246
Surface Roughness Mobility ….
1
 SR

E2
 SR
Parameter
6H
4H
SR (V/s)
1e13
5.82e14
4H SR Value is taken from Linewih (2002) paper
1
 SR

1
Cit
Effect of surface roughness is
negligible as compared to the effect of
interface traps on the total mobility.
Interface Trap Charge Mobility ….
1
C

nf  Nit
Temp
 T 


 300


ne

 1 
 screen_fit
screen_factor
 it
6H
4H
nf
5.4 x 1011
2.2 x 1012
Nit at RmT
~ 2 x 1012
~3 x 1012
it
1.5 x 1011
1.5 x 1011
screen_fit
1.5 x 1018
1 x 1018
screen_factor
0.8
0.7
Occupied interface trap density (Nit)
Ec
Qit  qNit  q  Dit E   f E dE
Ev
Dit = Density of traps per unit energy
f(E) is the probability density function. It is
directly proportional to the mobile charge
concentration (ne). Hence as MOSFET goes
towards stronger inversion, the occupied
interface trap density increases.
 E  Ec 
Dita E   Ditmid  Ditedge exp

a


f E  
1
1
 E  Ec 
1 Nc

exp
2 ne
k
T
 B 
4H SiC has a higher bandgap than 6H SiC (by 0.2eV). Ditedge value for 4H SiC
is obtained by extrapolating the Dit-E curve for 6H SiC by 0.1eV. This gives a
very high Ditedge value for 4H SiC because of the exponential relation
between Dit and E near the band edge. Hence 4H SiC has much higher
interface traps than 6H SiC.
Extrapolation of Dit-E curve for 6H SiC to get Dit-E
characteristics for 4H SiC
Final Dit-E curve for 4H that is used:
Dit_edge = 2.15 x 1013 cm-2eV-1
Dit_mid = 6.5 x 1011 cm-2eV-1
6H
4H
Ditmid (cm-2eV-1)
1 x 1013
2.19 x 1013
Ditedge (cm-2eV-1)
8 x 1011
8 x 1011
Nit vs. position for different Vgs.
T=27oC
Occupied interface trap
density increases with
increase in Vgs. This is
because the inversion layer
electron concentration
increases with increase in
Vgs causing more traps to
get filled
Device: 4H SiC MOSFET
W/L: 200 m / 200 m
Bias: Vgs = 2 to 4V Vds = 4V
Nit vs. position for different
Temperatures
Occupied interface trap
density decreases with
increase in temperature
because trapped electrons
can escape by gaining
sufficient energy at higher
temperatures.
So as the temperature
increases, effect of interface
trap charge decreases,
increasing overall mobility
Device: 4H SiC MOSFET
W/L: 200 m / 200 m
Bias: Vgs = 6V Vds = 1V
Comparing effects of Surface Roughness and
Interface traps at different Temperatures
The change in Id values for
a tenfold improvement of
the surface roughness
factor, is very small at all
three temperatures. Thus
surface roughness does
not change the current with
change in temperature.
The increase in current
with temperature is caused
by the reduction of filled
interface trap density as
temperature increases.
Device: 4H SiC MOSFET
W/L: 200 m / 200 m
Bias: Vgs = 6V Vds = 0-8V
Future Work…
• Better screening model based on BrooksHerring ionized impurity scattering model
• Surface roughness calculation to get proper
value for SR
• Fitting data at higher temperatures
• High power MOSFET simulation
• Investigating gate leakage in SiC MOSFETs
• Building a Graphical User Interface for the
simulator