Transcript Document
Review of Vertex Detector R&D for International Linear Collider • ILC • Vertex Detector R&D
- CCD (ISSI) - MAPS - DEPFET
• Summary
Jik Lee Seoul National Univ.
ACFA7 J. Lee
2020-05-01 1
International Linear Collider
electron and positron linear collider at energy from 500 GeV up to 1 TeV
and electron beam polarization > 80% and upgrade option for positron polarization Accelerator technology chosen:
3 Projects at
cold - DESY - Japan - US
( T eV E nergy S uperconducting L inear A ccelerator) ( G lobal L inear C ollider) ( N ext L inear C ollider )
SLAC CERN KEK
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▣ ILC Detectors
Main Tracker drives ILC detector configurations
Silicon Tracker Gaseous Tracker HUGE Medium/Large Large/Huge
5 tesla 4 tesla 3 tesla
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• Silicon based vertex detector(s):
CCD, MAPS, DEPFET, and more
- 4-5 cylindrical layers able to do stand alone tracking - background tolerance - fast (due to problem of overlapping events)
Beam Structures Warm bunch/train
ILC Environment for Vertex Detector
SVD in SD design 192 Cold 2820 train length bunch spacing train/s gap/train ACFA7 J. Lee 269 ns 1.4 ns 150/120 Hz 6.6 ms
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950 µs 337 ns 5 Hz
4
199 ms
ILC Vertex Detector Requirements
•
Close to IP
reduce extrapolation error
• Pixel Size:20x20 m
m 2
s
Point =3
m
m : ~800M channels
• Layer Thickness: <0.1%X
0 suppression of
g
conversions minimize multiple scattering LC environment requires vertex sensors which are substantially thinner and more precise than LHC and thus motivates new directions for R&D on vertex sensors
:
1/5 r bp , 1/30 pixel size, 1/3 thinner than LHC sensors ACFA7 J. Lee
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Vertex Detector R&D Groups
CCD
LCFI (Bristol, Glasgow, Lancaster, Liverpool, Oxford, RAL) : UK Niigata, KEK, Tohoku, Toyama : Japan Oregon, Yale, SLAC : US
MAPS
Strasbourg (IReS, LEPSI) + DAPNIA+DESY : France + Russia+Germany Brunel, Birmingham, CCLRC, Glasgow, Liverpool, RAL : UK
DEPFET
Bonn,MPI : Germany ACFA7 J. Lee
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Vertex Detector Comparison
Do not take this seriously.
It could be wrong due to my personal bias and ignorance!
CCD MAPS DEPFET Resolution
+ + -
Thin Material
+ + -
Rad. Hardness
+ +
Large Area Power Consum.
+ + + +
Readout speed
+ +
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CCD (Charge Coupled Device)
▪
charge collected in thin layer
▪ ▪
and transferred through silicon established technology excellent experience at SLD in SLC 300µm
40µm
• ~ 20 x 20 µm 2 pixels 800 M pixels - SLD: 300 M pixels • coordinate precision: 2-5 µm - SLD: 4 µm
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CCD Basics
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CCD Basics
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separate amplifier and readout for each column
CCD classic
CCD ISSUES
▪ faster readout needed for cold tech (50 µs) •
Column-Parallel CCD
with low noise - increase readout cycle of ~50MHz CP CCD ▪ need radiation hard • bulk damage induced CTI by n and e- being actively studied with possible countermeasures -
sacrificial charge
, faster r/o before trapping
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CCD Prototype (LCFI)
CPC1: prototype CP CCD by E2V noise ~ 100 e CPR1: CP readout ASIC by RAL designed for 50 MHz 250 parallel channels
750 x 400 pixels 20 m m pitch
CPC1+CPR1(bump-bonded): total noise ~ 140 e noise from preamps negligible
CPR1 CPR1
noise
• radiation effects on fast CCDs • detector-scale CCDs with ASIC and cluster finding logic - design underway and production this year
5.9 keV(1620e-) ACFA7 J. Lee
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CCD Radiation Study (KEK))
LED light makes sacrificial charge in CCD. It fills up traps and improve CTI VCTI is improved to a half of normal operation
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CCD Summary
• performance proven at SLD • good spacial resolution ( < 5µm) • improve slow readout speed
50 MHz CP readout • improve the radiation hardness
charge injection, notch structure • material reduction with unsupported silicon ACFA7 J. Lee
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Image Sensor with In-situ Storage (ISIS)
• 20 readouts/bunch train may be impossible due to beam –related RF pick up motivates delayed operation of detector for long bunch train: • charge collection to photogate from 20-30 µm silicon, as in a conventional CCD • signal charge shifted into storage register every 50 µs, providing required time slicing • string of signal charges is stored during bunch train in a buried channel, avoiding charge voltage conversion • totally noise-free charge storage, ready for readout in 200 ms of calm conditions between trains 2020-05-01 15
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Monolithic Active Pixel Sensors
~10-20µm • standard CMOS wafer • charge collection via thermal diffusion (no HV) • in epitaxial layer •“System on Chip” possible NO bump bonding
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APS2 chip (UK) • 4 pixel types, various flavours • Std 3MOS • 4MOS (CDS) [3T] [4T] • CPA (charge amp) • FAPS (10 deep pipeline) • 3MOS and 4MOS: 64 x 64, 15 m m pitch, 8 m m epi-layer MIP signal ~600 e-
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5.8 mm
3MOS des. A 3MOS des. B 3MOS des. C 3MOS des. D 3MOS des. E 4MOS des. A 4MOS des. B 4MOS des. C 4MOS des. D 4MOS des. E CPA des. A CPA des. B CPA des. C FAPS des. A FAPS des. B FAPS des. C FAPS des. D 3MOS des. F 4MOS des. F CPA des. D Column amplifiers
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Column decoder/control
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FAPS des. E
Design: R. Turchetta (RAL)
Radioactive source Tests on APS2 structures • • • seed pixel 3x3 cluster 5x5 cluster Event display spectrum • Out of 12 substructures 7 feature a S/N > 20 • Two structures problems in fabrication • Bad pixels: 1-2% • Preliminary results on irradiation up to 10 15 p/cm 2 promising
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Mimosa prototypes (France)
CHIP M1 M2 M3 M4 SUC 2 M5 & M5B M6 M7 M8 M9 SUC 1 YEAR 1999 2000 2001 2001 2003 2001/2003 2002 2003 2003 2004 PROCESS AMS 0.6
m
m MIETEC 0.35
m
m IBM 0.25
m
m AMS 0.35
m
m AMS 0.35
m
m AMS 0.6
m
m MIETEC 0.35
m
m AMS 0.35
m
m TSMC 0.25
m
m AMS 0.35 m EPITAXIAL
m
m 14 4,2 2 0 !
none 14 4,2 none 8 20 PITCH
m
m 20 20 8 20 40 17 28 25 25 20/30/40 METAL 3M 5M 3M 3M 3M 3M 5M 4M 5M 4M PECULIAR thick epitaxy thin epitaxy deep sub-
m
m low dop. Substrate low dop. Substrate (SUCIMA project) real scale 1M pixels col. // r.o. and integrated spars.
col. // r.o. and integ. spars. (photoFET) col. // r.o. and integrated spars.
opto. tests diodes/pitch/leakage current.
irradiation tests ACFA7 J. Lee
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MIMOSA-9
MIMOSA-9: 20,30,40 µm pitch with/without 20µm epi. layer Self-Bias, Pitch = 20 m m, diode 6 x 6 m m 2 Tested at CERN SPS-120 GeV pion beam 0.1% X 0 layer is achievable in thinning to 50µm: - Sensor back-thinned to 15µm
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MIMOSA-9 Results
SB with 20/30 m m pitch : eff ≥ 99.8% resolution ~ 1.5 m m @ 20 m m pitch A promising result since a high eff and a good resolution for a moderate granularity can not be for granted.
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MAPS Radiation Tolerance
• neutron irradiations - fluencies up to 10 12 neutrons/cm 2 are acceptable with considering LC requirements of ~ 10 9 n/ cm 2 /year • ionizing irradiations - tests up to a few 100kRad - exact sources of performance losses are under investigation (diode size and placements of the transistors are important parameters) 2020-05-01 22
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MAPS Summary
• • •
readout and sensor on one chip pixel size ~ CCD large area sensor and thinning (MIMOSA-9 tested OK)
> 99%, 20 µm pitch s ~ 2µm •
reasonable radiation hardness
• • •
fast readout (50 MHz possible, MIMOSA6:currently CDS takes time) R&D required to bring layer thickness down Optimize architecture for LC
Flexible APS (FAPS) architecture suitable for LC and fast imaging ACFA7 J. Lee
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FAPS
The in-pixel amp accesses the “Out” line, which is connected to all the pixels in a column
Relatively large capacitive load (>~pF) Relatively slow ACFA7 J. Lee
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The in-pixel amp accesses only local storage capacitors
Small capacitive load (<
Fast
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FAPS Design (RAL)
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mip
DEPleted Field Effect Transistor Sensors
+ + - + - - + - ACFA7 J. Lee DEPFET: detector + amplification property - high resistivity silicon substrate
-
fully depleted by sidewards depletion
full sensitivity over whole bulk
-
electrons collected in internal gate and modulate transistor current
-
internal gate can be reset by applying voltage to a dedicated contact
no reset noise - the first amplifying transistors are integrated directly into substrate and form pixel structure
a small input capacitance (~ 10fF)
very low noise operation can be achieved at room temp. (10 e-)
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DEPFET
• DEPFET collaboration: Bonn/MPI source top gate drain
MIP
clear bulk • p-channel MOS-FETs • double pixel structure (one source two drains) • pixel size 20x25µm 2 ~1µm p+ n+ p+ n+ n+ p n + + + n ▪ ▪ ▪ detector and amplification properties fully sensitivity over whole bulk very low noise operation at room temp.
p+ rear contact
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radiation hardness ?
large-area sensor?
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DEPFET Performance
Excellent noise performance with 55 Fe source spectrum Single pixel ACFA7 J. Lee Result at Room Temperature:
131 eV @ 5.9 keV
2.2 el. r.m.s.
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▣
Vertex Detector: DEPFET Prototype
• thinning process for sensors established
800x104 mm 2
- sensitive area 50µm thinned - fast signal to cope with high rate requirement - resolution of 9.5 µm
for single pixel ACFA7 J. Lee
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complete clear
no clear noise
-
(1 x clear) then sample 500x in 2.5ms
-
(clear + sample) 500x
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DEPFET Readout
• system integration of a 64x128 pixel matrix o steering chip (Switchers) tested up to 80 MHz o the read-out chip (the CURO) works up to 50/110 MHz (A/D): noise & threshold dispersion meets the specs Gate Switcher •
prototype system with DEPFET + CMOS matrix is assembled and working
CURO II •
designing and producing a 512 x 512 matrix is planned row wise selection with ACFA7 J. Lee
ADCs Reset Switcher I →U
DEPFET Summary
• excellent low noise performance at room temperature • low power consumption (saving material for cooling structure) • readout speed increasing • possibilities of thinning the sensor (20-30 μm) and readout chip • minimize pixel size • radiation hardness ACFA7 J. Lee
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Vertex Detector Comparison Now
Do not take this seriously.
It could be wrong due to my bias and ignorance!
CCD MAPS DEPFET Resolution
+ + 0
Thin Material
+ + -
Rad. Hardness
0 + +
Large Area
+ + ?
Power Consum.
+ 0 +
Readout speed
0 + +
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Summary
•
Intensive R&D in several VTX technologies with good world-wide communication going on!
• Premature choice of technology could seriously degrade the physics potential • Preferred technology(ies) to be selected on basis of full-size and fully operational prototype ladders (when?) ▪
Time Scale 2004 Cold technology chosen 2005 CDR for ILC (including first cost estimation) 2007 TDR for ILC 2008 site selection 2009 construction could start
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backups
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DEPFET Operation Mode
Pixel array readout scheme
:
Individual transistors or rows of transistors can be selected for readout while the other transistors are turned off.
Those are still able to collect signal charge
fast random access to specific
array regions very low power consumption ACFA7 J. Lee
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Overview: R/O Chip - CURO
CURO –
CU
rrent
R
ead
O
ut
current based readout
→ regulated cascode fixes input node • algebraic operations easy in current mode !
• automatic pedestal subtraction (fast CDS) • „on chip“ hit detection and zero suppression •
analog
r/o of hits
Spalte i cascode I sig I ped + I sig pedestal sub.
current buffer A current buffer B I sig current compare current FIFO cells 1/0 2x Output-MUX Hit-Finder HIT-FIFO hit-address: rowstamp, column serial-out outA outB hit
CURO I: prototype chip (05/2002) CURO II: 128 channel r/o chip (11/2003)
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Main parts :
• current memory cells • current comparator • hit finder 36