Transcript Reporting and Analysis of IBM`s CPU Measurement Facility Data

Reporting and Analysis of IBM’s
CPU Measurement Facility Data
Philadelphia CMG
September 14, 2012
Bill Shelden
[email protected]
Topics
• Introduction
• CPU Measurement Facility
• Using the SMF 113 records
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Data from a 2097-706 (z10)
Relative Nest Intensity
Matching LSPR Workloads (LOW, AVG, HIGH)
Data from a 2818-Y02 (z114)
MIPS Reasonability Check
CPU Capacity Planning Checklist
Conclusions
PerfTechPro Offer
References
• CPU MF - 2012 Update and WSC Experiences for SHARE
Atlanta Final.pdf
• CPU MF Webinar Part 1 May 2 Final.pdf
• CPU MF Webinar Part 2 June 14 Final.pdf
• Peter.Enrico.Exploring.SMF113.and.CPU.Counters.pdf
• SA23-2260-02 The Load-Program-Parameter and the
CPU-Measurement Facilities.pdf
• SA23-2261-01 IBM The CPU-Measurement Facility
Extended Counters Definition for z10 and z196.pdf
Introduction - CPU Measurement Facility
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Introduced in z10 and later processors
New facility that provides hardware instrumentation data for production
systems
Two Major components
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Counters
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Sampling
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Gathered on an LPAR basis
Writes SMF 113 records
New z/VM Monitor Records
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Instruction time-in-CSECT
New z/OS HIS started task
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Cache and memory hierarchy information
SCPs supported include z/OS and z/VM
Gathered on an LPAR basis – all guests are aggregated
Writes new Domain 5 (Processor) Record 13 (CPU MF Counters) records
Minimal overhead
Introduction – Using the SMF113 records
• Counters are cumulative
• Need to compute deltas between records
• Cut on the SMF accounting interval
• Not the RMF interval
• Records pertain to a specific LPAR
Data from a 2097-706 (z10)
Cycles Per Instruction
Level 1 Miss %
% of L1 Misses Sourced from Memory
Instruction Sourcing Profile (of L1 Misses)
Relative Nest Intensity
Relative Nest Intensity
• Some Definitions:
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L2LP = % from Level 2 Local cache (same book)
L2RP = % from Level 2 Remote cache (different book)
L3P = % from Level 3 cache
L4LP = % from Level 5 Local cache (same book)
L4RP = % from Level 4 Remote cache (different book)
MEMP = % sourced from Memory
• RNI - Reflects the distribution and latency of sourcing
from shared caches and memory
• For z10 EC and BC:
• RNI = (1.0*L2LP + 2.4*L2RP + 7.5*MEMP) / 100
• For z196 / z114:
• RNI = 1.6*(0.4*L3P + 1.0*L4LP + 2.4*L4RP + 7.5*MEMP) / 100
RNI-based LSPR Workload Decision Table
L1MP < 3%
RNI>0.75
RNI<0.75
AVERAGE
LOW
3%<L1MP<6%
RNI>1.0
0.6<RNI<1.0
RNI<0.6
HIGH
AVERAGE
LOW
L1MP>6%
RNI>0.75
RNI<0.75
HIGH
AVERAGE
Matching LSPR Workloads (LOW, AVG, HIGH)
Data from a 2818-Y02 (z114)
Cycles Per Instruction
Level 1 Miss %
% of L1 Misses Sourced from Memory
Instruction Sourcing Profile (of L1 Misses)
Matching LSPR Workloads (LOW, AVG, HIGH)
RNI may be Load dependent
Relative Nest Intensities
SYSB (2818-Y02)
3.50
3.00
MIPS Used
SYSA (2097-706)
SYSB (2818-Y02)
1200
1000
2.50
800
2.00
600
1.50
400
1.00
0.50
0.00
200
0
SYSA (2097-706)
Relative Nest Intensity
MIPS Reasonability Check
MIPS Reasonability Check
• From CPU Table (LOW RNI)
• GPP ‘MIPS’ = 5045.60
• ‘MIPS’/GPP = 5045.60 / 6 = 841 ‘MIPS’/GPP
• For 9:59 AM which is a LOW RNI interval
• 3.54 Cycles per Instruction
• 4.4 Cycles per nanosecond (per GPP)
• 4.4 / 3.54 = 1.24 Instructions per Nanosecond
• 1.24 x 1,000,000,000 Instructions per Second
• 1.24 x 1000 = 1240 MIPS/GPP
CPU Capacity Planning Checklist
• Collect CPU Measurement Facility Data for
all ‘important’ LPARs
• For each LPAR:
• Determine RNI-based LSPR workload mix among
LOW, AVG or HIGH
• Determine MIPS values for current and
contemplated CPUs based on RITRs for RNIbased LSPR workload mix just determined
• Use IBM’s zPCR to account for specific LPAR
configuration
Conclusions
• Great insights into hardware and
workload relationship
• RNI May be load dependent
• More accurate CPU capacity planning
PerfTechPro Offer
• Send us some of your data:
• 24 hours of data
• RMF 70, 71, 72, 73, and 75s
• SMF 113s from one LPAR
• We will:
• Return a set of charts in a PDF
• Discuss your results on a WebEx
• Contact Bill Hart at [email protected]