Transcript DP049: Introduction and Five Components of a Computer

Computer Architecture
Chapter 5
The Processor: Datapath and Control
Lec5.1
Contents
 Overview & Review
 Implementation
• Functional Unit
• Datapath
• Control
 Single Cycle & Multicycle Approach
 Implementing the Control
• PLA, ROM
• Microprogramming
Chap 5.2
The Big Picture: Where are We Now?
 The Five Classic Components of a Computer
Processor
Input
Control
Memory
Datapath
Output
 Today’s Topic: Design a Single Cycle Processor
machine
design
inst. set design
Arithmetic
technology
Chap 5.3
The Processor: Datapath & Control
 We're ready to look at an implementation of the MIPS
 Simplified to contain only:
• memory-reference instructions: lw, sw
• arithmetic-logical instructions: add, sub, and, or, slt
• control flow instructions: beq, j
 Generic Implementation:
•
•
•
•
use the program counter (PC) to supply instruction address
get the instruction from memory
read registers
use the instruction to decide exactly what to do
 All instructions use the ALU after reading the registers
• memory-reference: address calculation
• arithmetic-logic: arithmetic logic execution
• control flow: comparison
Chap 5.4
The MIPS Instruction Formats
 All MIPS instructions are 32 bits long. The three
instruction formats:
31
• R-type
26
op
rs
6 bits
• I-type
31
26
op
31
16
rt
5 bits
5 bits
21
rs
6 bits
• J-type
21
5 bits
11
6
0
rd
shamt
funct
5 bits
5 bits
6 bits
16
0
address/immediate
rt
5 bits
16 bits
26
op
6 bits
0
target address
26 bits
 The different fields are:
• op: operation of the instruction
• rs, rt, rd: the source and destination register specifiers
• shamt: shift amount
• funct: selects the variant of the operation in the “op” field
• address / immediate: address offset or immediate value
• target address: target address of the jump instruction
Chap 5.5
The MIPS-lite Subset for today
 ADD and SUB
• addU rd, rs, rt
• subU rd, rs, rt
31
op
31
21
rs
6 bits
 OR Immediate:
• ori rt, rs, imm16
26
op
rt
5 bits
26
5 bits
21
rs
6 bits
16
6
0
rd
shamt
funct
5 bits
5 bits
6 bits
16
rt
5 bits
11
0
immediate
5 bits
16 bits
 LOAD and STORE Word
• lw rt, rs, imm16
• sw rt, rs, imm16
31
op
31
21
rs
6 bits
 BRANCH:
• beq rs, rt, imm16
26
op
6 bits
rt
5 bits
26
16
rs
5 bits
immediate
5 bits
21
0
16 bits
16
rt
5 bits
0
immediate
16 bits
Chap 5.6
More Implementation Details
 Abstract / Simplified View:
Data
PC
Address
Instruction
memory
Instruction
Register #
Registers
ALU
Address
Register #
Data
memory
Register #
Data
 Two types of functional units:
• elements that operate on data values (combinational)
• elements that contain state (sequential)
Chap 5.7
State Elements
 Unclocked vs. Clocked
 Clocks used in synchronous logic
•
when should an element that contains state be updated?
falling edge
cycle time
rising edge
Chap 5.8
An unclocked state element
 The set-reset latch
• output depends on present inputs and also on past inputs
Chap 5.9
Latches and Flip-flops
 Output is equal to the stored value inside the element
(don't need to ask for permission to look at the value)
 Change of state (value) is based on the clock
 Latches: whenever the inputs change, and the clock is asserted
(level-sensitive methodology)
 Flip-flop: state changes only on a clock edge
(edge-triggered methodology)
Chap 5.10
D-latch
 Two inputs:
• the data value to be stored (D)
• the clock signal (C) indicating when to read & store D
 Two outputs:
• the value of the internal state (Q) and it's complement
C
Q
D
C
_
Q
D
Q
Chap 5.11
D flip-flop
 Output changes only on the clock edge
D
D
C
D
latch
Q
D
Q
D
latch _
C
Q
Q
_
Q
C
D
C
Q
Chap 5.12
Implementation
 An edge triggered methodology
 Typical execution:
• read contents of some state elements,
• send values through some combinational logic
• write results to one or more state elements
State
element
1
Combinational logic
State
element
2
Clock cycle
Chap 5.13
Register File
 Built using D flip-flops
Read register
number 1
Register 0
Register 1
Register n – 1
M
u
x
Read register
number 1
Read data 1
Read
data 1
Read register
number 2
Register n
Register file
Write
register
Read register
number 2
Write
data
M
u
x
Read
data 2
Write
Read data 2
Chap 5.14
Register File
 Note: we still use the real clock to determine when to write
Write
0
Register number
C
Register 0
1
D
n-to-1
decoder
C
n– 1
Register 1
D
n
C
Register n – 1
D
C
Register n
Register data
D
Chap 5.15
Simple Implementation
 Include the functional units we need for each instruction
Instruction
address
PC
Instruction
Add Sum
Instruction
memory
MemWrite
a. Instruction memory
5
Register
numbers
5
5
Data
b. Program counter
3
Read
register 1
Read
register 2
Registers
Write
register
Write
data
c. Adder
ALU control
Read
data 1
Data
Zero
ALU ALU
result
Read
data 2
Address
Write
data
Read
data
Data
memory
16
Sign
extend
32
MemRead
a. Data memory unit
b. Sign-extension unit
Why do we need this stuff?
RegWrite
a. Registers
b. ALU
Chap 5.16
Datapath for Instruction fetch and program counter increment
Add
4
PC
Read
address
Instruction
Instruction
memory
Chap 5.17
Datapath for R type instruction
3
Read
register 1
Instruction
Read
register 2
Registers
Write
register
Write
data
ALU operation
Read
data 1
Zero
ALU ALU
result
Read
data 2
RegWrite
Chap 5.18
Datapath for lw and sw instructions
3
Read
register 1
Instruction
Read
register 2
Registers
Write
register
Write
data
ALU operation
MemWrite
Read
data 1
Zero
ALU ALU
result
Address
Read
data 2
Write
data
RegWrite
16
Sign
extend
32
Read
data
Data
memory
MemRead
Chap 5.19
Datapath for branch instruction
PC + 4 from instruction datapath
Add Sum
Branch target
Shift
left 2
Instruction
3
Read
register 1
Read
register 2
Registers
Write
register
Write
data
ALU operation
Read
data 1
ALU Zero
To branch
control logic
Read
data 2
RegWrite
16
Sign
extend
32
Chap 5.20
Datapath for memory and R-type instructions
 Use multiplexors to stitch them together
Chap 5.21
Datapath with instuction fetch
Add
4
PC
Read
address
Instruction
Instruction
memory
Registers
Read
register 1
Read
Read
data
1
register 2
3
Write
data
M
u
x
Zero
ALU ALU
result
Address
Write
data
RegWrite
16
MemWrite
MemtoReg
ALUSrc
Read
data 2
Write
register
ALU operation
Sign 32
extend
Read
data
Data
memory
MemRead
Chap 5.22
M
u
x
Building the overall datapath
 Use multiplexors to stitch them together
PCSrc
M
u
x
Add
Add ALU
result
4
Shift
left 2
Registers
PC
Read
address
Instruction
Instruction
memory
Read
register 1
Read
Read
data 1
register 2
Write
register
Write
data
RegWrite
16
ALUSrc
Read
data 2
Sign
extend
M
u
x
3
ALU operation
Zero
ALU ALU
result
MemWrite
MemtoReg
Address
Read
data
Data
memory
Write
data
M
u
x
32
MemRead
Chap 5.23
Control
 Selecting the operations to perform (ALU, read/write, etc.)
 Controlling the flow of data (multiplexor inputs)
 Information comes from the 32 bits of the instruction
 Example:
add $8, $17, $18
Instruction Format:
000000
10001
10010
01000
op
rs
rt
rd
00000 100000
shamt
funct
 ALU's operation based on instruction type and function code
Chap 5.24
Control
 e.g., what should the ALU do with this instruction
 Example: lw $1, 100($2)
35
2
1
op
rs
rt
100
16 bit offset
 ALU control input
000
001
010
110
111
AND
OR
add
subtract
set-on-less-than
 Why is the code for subtract 110 and not 011?
Chap 5.25
Control
 Must describe hardware to compute 3-bit ALU conrol input
• given instruction type
00 = lw, sw
01 = beq,
11 = arithmetic
• function code for arithmetic
ALUOp
computed from instruction type
 ALU control
OP code
ALU op
Inst. operation Function field ALU operation ALU control
LW
00
load word
xxxxxx
add
010
SW
00
store word
xxxxxx
add
010
Branch equal
01
branch equal
xxxxxx
subtract
110
R-type
11
add
100000
add
010
R-type
11
subtract
100010
subtract
110
R-type
11
AND
100100
and
000
R-type
11
OR
100101
or
001
R-type
11
set on less than
101010
set on less than
111
Chap 5.26
Control
 Describe it using a truth table (can turn into gates):
ALUOp
ALUOp1 ALUOp0
0
0
X
1
1
X
1
X
1
X
1
X
1
X
F5
X
X
X
X
X
X
X
Funct field
F4 F3 F2 F1
X X X X
X X X X
X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 0
X 1 0 1
Operation
F0
X
X
0
0
0
1
0
010
110
010
110
000
001
111
Chap 5.27
Control
PCSrc
Add
ALU
Add result
4
Shift
left 2
RegWrite
Instruction [25– 21]
PC
Read
address
Instruction
[31– 0]
Instruction
memory
Instruction [20– 16]
1
M
u
Instruction [15– 11] x
0
RegDst
Instruction [15– 0]
Read
register 1
Read
register 2
Read
data 1
MemWrite
ALUSrc
Read
Write
data 2
register
Write
Registers
data
16
Sign
extend
1
M
u
x
0
1
M
u
x
0
Zero
ALU ALU
result
MemtoReg
Address
Write
data
32
ALU
control
Read
data
Data
memory
MemRead
Instruction [5– 0]
ALUOp
Chap 5.28
1
M
u
x
0
Control
0
M
u
x
Add
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Instruction [15– 11]
1
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
ALU
result
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Address
Write
data
Instruction [15– 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5– 0]
Memto- Reg Mem Mem
Instruction RegDst ALUSrc
Reg
Write Read Write Branch ALUOp1 ALUp0
R-format
1
0
0
1
0
0
0
1
0
lw
0
1
1
1
1
0
0
0
0
sw
X
1
X
0
0
1
0
0
0
beq
X
0
X
0
0
0
1
0
1
Chap 5.29
Control
 Simple combinational logic (truth tables)
Inputs
Op5
ALUOp
Op4
ALU control block
Op3
Op2
ALUOp0
Op1
ALUOp1
F3
F2
F (5– 0)
Op0
Operation2
Operation1
F1
Operation
R-format
Iw
sw
beq
RegDst
ALUSrc
MemtoReg
Operation0
F0
Outputs
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
Chap 5.30
Our Simple Control Structure
 All of the logic is combinational
 We wait for everything to settle down, and the right thing to be
done
• ALU might not produce right answer right away
• we use write signals along with clock to determine when to write
 Cycle time determined by length of the longest path
State
element
1
Combinational logic
State
element
2
Clock cycle
We are ignoring some details like setup and hold times
Chap 5.31
Single Cycle Implementation
 Calculate cycle time assuming negligible delays except:
• memory (2ns), ALU and adders (2ns), register file access (1ns)
PCSrc
Add
ALU
Add result
4
RegWrite
Instruction [25– 21]
PC
Read
address
Instruction
[31– 0]
Instruction
memory
Instruction [20– 16]
1
M
u
Instruction [15– 11] x
0
RegDst
Instruction [15– 0]
Read
register 1
Read
register 2
Read
data 1
Read
Write
data 2
register
Write
data Registers
16
Sign 32
extend
1
M
u
x
0
Shift
left 2
MemWrite
ALUSrc
1
M
u
x
0
ALU
control
Zero
ALU ALU
result
MemtoReg
Address
Read
data
Write Data
data memory
1
M
u
x
0
MemRead
Instruction [5– 0]
ALUOp
Chap 5.32
Where we are headed
 Single Cycle Problems:
• what if we had a more complicated instruction like floating point?
• wasteful of area
 One Solution:
• use a smaller cycle time
• have different instructions take different numbers of cycles
• a multicycle datapath:
Instruction
register
PC
Address
Data
A
Register #
Instruction
Memory
or data
Data
Memory
data
register
ALU
Registers
Register #
ALUOut
B
Register #
Chap 5.33
Multicycle Approach
 We will be reusing functional units
• ALU used to compute address and to increment PC
• Memory used for instruction and data
 Our control signals will not be determined solely by
instruction
• e.g., what should the ALU do for a subtract instruction?
 We’ll use a finite state machine for control
Chap 5.34
Review: finite state machines
 Finite state machines:
• a set of states and
• next state function (determined by current state and the input)
• output function (determined by current state and possibly input)
Current state
Next-state
function
Next
state
Clock
Inputs
Output
function
Outputs
• We’ll use a Moore machine (output based only on current state)
Chap 5.35
Review: finite state machines
 Example:
B. 21 A friend would like you to build an electronic eye for use as a
fake security device. The device consists of three lights lined up in a
row, controlled by the outputs Left, Middle, and Right, which, if
asserted, indicate that a light should be on. Only one light is on at a
time, and the light moves from left to right and then from right to left,
thus scaring away thieves who believe that the device is monitoring
their activity. Draw the graphical representation for the finite state
machine used to specify the electronic eye. Note that the rate of the
eye’s movement will be controlled by the clock speed (which should
not be too great) and that there are essentially no inputs.
Chap 5.36
Multicycle Approach
 Break up the instructions into steps, each step takes a
cycle
• balance the amount of work to be done
• restrict each cycle to use only one major functional unit
 At the end of a cycle
• store values for use in later cycles (easiest thing to do)
• introduce additional internal registers
PC
0
M
u
x
1
Address
Memory
MemData
Write
data
Instruction
[25– 21]
Read
register 1
Instruction
[20– 16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Instruction
[15– 0]
Instruction
register
Instruction
[15– 0]
Memory
data
register
0
M
Instruction u
x
[15– 11]
1
A
B
4
Write
data
0
M
u
x
1
16
Sign
extend
0
M
u
x
1
32
Zero
ALU ALU
result
ALUOut
0
1M
u
2 x
3
Shift
left 2
Chap 5.37
PCSrc
Add
ALU
Add result
4
Shift
left 2
RegWrite
Instruction [25– 21]
PC
Read
address
Instruction
[31– 0]
Instruction
memory
Read
register 1
Read
register 2
Instruction [20– 16]
1
M
u
Instruction [15– 11] x
0
Read
data 1
MemWrite
ALUSrc
Read
data 2
1
M
u
x
0
Write
register
Write
Registers
data
RegDst
Instruction [15– 0]
16
1
M
u
x
0
Zero
ALU ALU
result
Address
Write
data
32
Sign
extend
MemtoReg
ALU
control
Read
data
Data
memory
1
M
u
x
0
MemRead
Instruction [5– 0]
ALUOp
PC
0
M
u
x
1
Address
Memory
MemData
Write
data
Instruction
[25– 21]
Read
register 1
Instruction
[20– 16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Instruction
[15– 0]
Instruction
register
Instruction
[15– 0]
Memory
data
register
0
M
Instruction u
x
[15– 11]
1
A
B
4
Write
data
0
M
u
x
1
16
Sign
extend
0
M
u
x
1
32
Zero
ALU ALU
result
ALUOut
0
1 M
u
2 x
3
Shift
left 2
Chap 5.38
Five Execution Steps
 Instruction Fetch
 Instruction Decode and Register Fetch
 Execution, Memory Address Computation, or Branch
Completion
 Memory Access or R-type instruction completion
 Write-back step
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
Chap 5.39
Step 1: Instruction Fetch
 Use PC to get instruction and put it in the Instruction
Register.
 Increment the PC by 4 and put the result back in the PC.
 Can be described succinctly using RTL "Register-Transfer
Language"
IR = Memory[PC];
PC = PC + 4;
Chap 5.40
Step 2: Instruction Decode and Register Fetch
 Read registers rs and rt in case we need them
 Compute the branch address in case the instruction is a
branch
 RTL:
A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);
 We aren't setting any control lines based on the
instruction type
(we are busy "decoding" it in our control logic)
Chap 5.41
Step 3 (instruction dependent)
 ALU is performing one of three functions, based on
instruction type
 Memory Reference:
ALUOut = A + sign-extend(IR[15-0]);
 R-type:
ALUOut = A op B;
 Branch:
if (A==B) PC = ALUOut;
Chap 5.42
Step 4 (R-type or memory-access)
 Loads and stores access memory
MDR = Memory[ALUOut];
or
Memory[ALUOut] = B;
 R-type instructions finish
Reg[IR[15-11]] = ALUOut;
The write actually takes place at the end of the cycle on
the edge
Chap 5.43
Write-back step
 Reg[IR[20-16]]= MDR;
What about all the other instructions?
Chap 5.44
Summary:
Step name
Instruction fetch
Action for R-type
instructions
Instruction
decode/register fetch
Action for memory-reference
Action for
instructions
branches
IR = Memory[PC]
PC = PC + 4
A = Reg [IR[25-21]]
B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address
computation, branch/
jump completion
ALUOut = A op B
ALUOut = A + sign-extend
(IR[15-0])
Memory access or R-type
completion
Reg [IR[15-11]] =
ALUOut
Load: MDR = Memory[ALUOut]
or
Store: Memory [ALUOut] = B
Memory read completion
if (A ==B) then
PC = ALUOut
Action for
jumps
PC = PC [31-28] II
(IR[25-0]<<2)
Load: Reg[IR[20-16]] = MDR
Chap 5.45
Simple Questions
 How many cycles will it take to execute this code?
lw $t2, 0($t3)
lw $t3, 4($t3)
beq $t2, $t3, Label
#assume not
add $t5, $t2, $t3
sw $t5, 8($t3)
Label: ...
 What is going on during the 8th cycle of execution?
 In what cycle does the actual addition of $t2 and $t3
takes place?
Chap 5.46
Implementing the Control
 Value of control signals is dependent upon:
• what instruction is being executed
• which step is being performed
 Use the information we’re accumulated to specify a finite
state machine
• specify the finite state machine graphically, or
• use microprogramming
 Implementation can be derived from specification
Chap 5.47
Graphical Specification of FSM
Instruction decode/
register fetch
Instruction fetch
(Op
2
or
W ')
= 'L
(Op
W
= 'S
6
Branch
completion
EQ
')
e)
-t y p
R
=
'B
(Op
')
Execution
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
8
ALUSrcA =1
ALUSrcB = 00
ALUOp = 10
Jump
completion
9
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSource = 01
PCWrite
PCSource = 10
(O
p
=
'S
')
W
(Op = 'LW')
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
(Op = 'J')
Memory address
computation
1
=
Start
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
(O
p
0
Memory
access
3
Memory
access
5
MemRead
IorD = 1
R-type completion
7
MemWrite
IorD = 1
RegDst = 1
RegWrite
MemtoReg = 0
Write-back step
4
RegDst = 0
RegWrite
MemtoReg = 1
 How many state bits will we need?
Chap 5.48
Finite State Machine for Control
 Implementation:
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
Control logic
MemtoReg
PCSource
ALUOp
Outputs
ALUSrcB
ALUSrcA
RegWrite
RegDst
NS3
NS2
NS1
NS0
Instruction register
opcode field
S0
S1
S2
S3
Op0
Op1
Op2
Op3
Op4
Op5
Inputs
State register
Chap 5.49
PLA Implementation
 If I picked a horizontal or vertical line could you explain it?
Op5
Op4
Op3
Op2
Op1
Op0
S3
S2
S1
S0
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
MemtoReg
PCSource1
PCSource0
ALUOp1
ALUOp0
ALUSrcB1
ALUSrcB0
ALUSrcA
RegWrite
RegDst
NS3
NS2
NS1
NS0
Chap 5.50
ROM Implementation
 ROM = "Read Only Memory"
• values of memory locations are fixed ahead of time
 A ROM can be used to implement a truth table
• if the address is m-bits, we can address 2m entries in the ROM.
• our outputs are the bits of data that the address points to.
m
n
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
m is the "height", and n is the "width"
Chap 5.51
ROM Implementation
 How many inputs are there?
6 bits for opcode, 4 bits for state = 10 address lines
(i.e., 210 = 1024 different addresses)
 How many outputs are there?
16 datapath-control outputs, 4 state bits = 20
outputs
 ROM is 210 x 20 = 20K bits (and a rather unusual size)
 Rather wasteful, since for lots of the entries, the outputs
are the same
- i.e., opcode is often ignored
Chap 5.52
ROM vs PLA
 Break up the table into two parts
- 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM
- 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM
- Total: 4.3K bits of ROM
 PLA is much smaller
- can share product terms
- only need entries that produce an active output
- can take into account don't cares
 Size is (#inputs x #product-terms) + (#outputs x #product-terms)
For this example = (10x17)+(20x17) = 460 PLA cells
 PLA cells usually about the size of a ROM cell (slightly bigger)
Chap 5.53
Another Implementation Style
 Complex instructions: the "next state" is often current
state + 1
Control unit
PLA or ROM
Outputs
Input
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
BWrite
MemtoReg
PCSource
ALUOp
ALUSrcB
ALUSrcA
RegWrite
RegDst
AddrCtl
1
State
Adder
Op[5– 0]
Address select logic
Instruction register
opcode field
Chap 5.54
Details
Op
000000
000010
000100
100011
101011
Dispatch ROM 1
Opcode name
R-format
jmp
beq
lw
sw
Value
0110
1001
1000
0010
0010
Dispatch ROM 2
Opcode name
lw
sw
Op
100011
101011
Value
0011
0101
PLA or ROM
1
State
Adder
3
Mux
2 1
AddrCtl
0
0
Dispatch ROM 2
Dispatch ROM 1
Op
Address select logic
Instruction register
opcode field
State number
0
1
2
3
4
5
6
7
8
9
Address-control action
Use incremented state
Use dispatch ROM 1
Use dispatch ROM 2
Use incremented state
Replace state number by 0
Replace state number by 0
Use incremented state
Replace state number by 0
Replace state number by 0
Replace state number by 0
Value of AddrCtl
3
1
2
3
0
0
3
0
0
0
Chap 5.55
Microprogramming
Control unit
Microcode memory
Outputs
Input
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
BWrite
MemtoReg
PCSource
ALUOp
ALUSrcB
ALUSrcA
RegWrite
RegDst
AddrCtl
Datapath
1
Microprogram counter
Adder
Op[5– 0]
Address select logic
Instruction register
opcode field
 What are the Microinstructions??
Chap 5.56
Microprogramming
 A specification methodology
• appropriate if hundreds of opcodes, modes, cycles, etc.
• signals specified symbolically using microinstructions
Label
Fetch
Mem1
LW2
ALU
control
Add
Add
Add
Register
control
SRC1 SRC2
PC
4
PC
Extshft Read
A
Extend
Memory
Read PC
PCWrite
control
ALU
Read ALU
Write MDR
SW2
Rformat1 Func code A
Write ALU
B
Write ALU
BEQ1
JUMP1
Subt
A
B
ALUOut-cond
Jump address
Sequencing
Seq
Dispatch 1
Dispatch 2
Seq
Fetch
Fetch
Seq
Fetch
Fetch
Fetch
 Will two implementations of the same architecture have
the same microcode?
 What would a microassembler do?
Chap 5.57
Microinstruction format
Field name
ALU control
SRC1
SRC2
Value
Add
Subt
Func code
PC
A
B
4
Extend
Extshft
Read
ALUOp = 10
ALUSrcA = 0
ALUSrcA = 1
ALUSrcB = 00
ALUSrcB = 01
ALUSrcB = 10
ALUSrcB = 11
Write ALU
RegWrite,
RegDst = 1,
MemtoReg = 0
RegWrite,
RegDst = 0,
MemtoReg = 1
MemRead,
lorD = 0
MemRead,
lorD = 1
MemWrite,
lorD = 1
PCSource = 00
PCWrite
PCSource = 01,
PCWriteCond
PCSource = 10,
PCWrite
AddrCtl = 11
AddrCtl = 00
AddrCtl = 01
AddrCtl = 10
Register
control
Write MDR
Read PC
Memory
Read ALU
Write ALU
ALU
PC write control
ALUOut-cond
jump address
Sequencing
Signals active
ALUOp = 00
ALUOp = 01
Seq
Fetch
Dispatch 1
Dispatch 2
Comment
Cause the ALU to add.
Cause the ALU to subtract; this implements the compare for
branches.
Use the instruction's function code to determine ALU control.
Use the PC as the first ALU input.
Register A is the first ALU input.
Register B is the second ALU input.
Use 4 as the second ALU input.
Use output of the sign extension unit as the second ALU input.
Use the output of the shift-by-two unit as the second ALU input.
Read two registers using the rs and rt fields of the IR as the register
numbers and putting the data into registers A and B.
Write a register using the rd field of the IR as the register number and
the contents of the ALUOut as the data.
Write a register using the rt field of the IR as the register number and
the contents of the MDR as the data.
Read memory using the PC as address; write result into IR (and
the MDR).
Read memory using the ALUOut as address; write result into MDR.
Write memory using the ALUOut as address, contents of B as the
data.
Write the output of the ALU into the PC.
If the Zero output of the ALU is active, write the PC with the contents
of the register ALUOut.
Write the PC with the jump address from the instruction.
Choose the next microinstruction sequentially.
Go to the first microinstruction to begin a new instruction.
Dispatch using the ROM 1.
Dispatch using the ROM 2.
Chap 5.58
Maximally vs. Minimally Encoded
 No encoding:
•
1 bit for each datapath operation
•
faster, requires more memory (logic)
•
used for Vax 780 ?an astonishing 400K of memory!
 Lots of encoding:
•
send the microinstructions through logic to get control signals
•
uses less memory, slower
 Historical context of CISC:
•
Too much logic to put on a single chip with everything else
•
Use a ROM (or even RAM) to hold the microcode
•
It’s easy to add new instructions
Chap 5.59
Microcode: Trade-offs

Distinction between specification and implementation is sometimes blurred

Specification Advantages:


•
Easy to design and write
•
Design architecture and microcode in parallel
Implementation (off-chip ROM) Advantages
•
Easy to change since values are in memory
•
Can emulate other architectures
•
Can make use of internal registers
Implementation Disadvantages, SLOWER now that:
•
Control is implemented on same chip as processor
•
ROM is no longer faster than RAM
•
No need to go back and make changes
Chap 5.60
The Big Picture
Initial
representation
Finite state
diagram
Microprogram
Sequencing
control
Explicit next
state function
Microprogram counter
+ dispatch ROMS
Logic
representation
Logic
equations
Truth
tables
Implementation
technique
Programmable
logic array
Read only
memory
Chap 5.61