Transcript Pipelined Datapath and Control

Pipelined Datapath and Control
Lecture for CPSC 5155
Edward Bosworth, Ph.D.
Computer Science Department
Columbus State University
§4.6 Pipelined Datapath and Control
MIPS Pipelined Datapath
MEM
Right-to-left
flow leads to
hazards
WB
Chapter 4 — The Processor — 2
Pipeline registers

Need registers between stages

To hold information produced in previous cycle
Chapter 4 — The Processor — 3
The Pipeline Registers
• IF/ID This provides an execution context for the ID
(Instruction Decode and Register Fetch) stage of execution.
• ID/EX This provides an execution context for the EX
(Execute) phase of instruction execution. In particular, the
discrete control signals generated by the control unit as a
result of instruction decoding are stored here.
• EX/MEM This provides an execution context for the MEM
(Memory Access or R-Type Instruction Completion) phase
of instruction execution. In addition , this register stores
copies of the control signals required to complete both the
MEM and WB phase of execution for this instruction.
• MEM/WB This provides an execution context for the WB
(Write Back) phase of instruction execution.
Pipeline Operation

Cycle-by-cycle flow of instructions through
the pipelined datapath
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“Single-clock-cycle” pipeline diagram
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c.f. “multi-clock-cycle” diagram
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Shows pipeline usage in a single cycle
Highlight resources used
Graph of operation over time
We’ll look at “single-clock-cycle” diagrams
for load & store
Chapter 4 — The Processor — 5
IF for Load, Store, …
Chapter 4 — The Processor — 6
ID for Load, Store, …
Chapter 4 — The Processor — 7
EX for Load
Chapter 4 — The Processor — 8
MEM for Load
Chapter 4 — The Processor — 9
WB for Load
Wrong
register
number
Chapter 4 — The Processor — 10
Corrected Datapath for Load
Chapter 4 — The Processor — 11
EX for Store
Chapter 4 — The Processor — 12
MEM for Store
Chapter 4 — The Processor — 13
WB for Store
Chapter 4 — The Processor — 14
Multi-Cycle Pipeline Diagram

Form showing resource usage
Chapter 4 — The Processor — 15
Multi-Cycle Pipeline Diagram

Traditional form
Chapter 4 — The Processor — 16
Single-Cycle Pipeline Diagram
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State of pipeline in a given cycle
Chapter 4 — The Processor — 17
Pipelined Control (Simplified)
Chapter 4 — The Processor — 18
Pipelined Control

Control signals derived from instruction
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As in single-cycle implementation
Chapter 4 — The Processor — 19
The Control Signals by Phase
• Instruction Fetch There are no control signals specific to
this stage.
• Instruction Decode There are no instruction–specific
control signals in this step.
• Execute
• There are three control signals associated with this step.
• RegDst This selects which field, IR[20:16] or IR[15:11] will
be used as the register destination number for the Write
Register in WB. The five bit value selected is written into
EX/MEM and copied to MEM/WB.
• ALUOp This is the two–bit selector of the ALU operation.
• ALUSrc This discrete control signal selects the B input to
the ALU.
Control Signals by Phase
•
•
•
•
•
•
•
•
•
Memory Access
There are three control signals associated with this step.
Branch
This indicates that a branch instruction is in this stage.
MemRead
The ALU output is used as a memory address that is read.
This is set by the LW instruction.
MemWrite The ALU output is used as a memory address, to which
the contents of the specified register are written.
This is set by the SW instruction.
Write Back
There are two control signals associated with this step.
MemToReg This selects either the ALU output or memory output to
be written back to the register file
RegWrite
This causes the selected value to be written to the
specified register.
Pipelined Control
Chapter 4 — The Processor — 22
Size of the Pipeline Registers
Program Counter
Machine Language Instruction
Register 1 Read Data
Register 2 Read Data
Sign Extended Address Offset
Discrete Control Signals
ALU Function Code
Shift Amount
ALU Result
ALU Discrete Output: Zero
Data read from memory
Destination Register Number
TOTAL BITS
IF/ID
32
32
ID/EX
32
32
32
32
9
6
5
64
10
158
EX/MEM
32
MEM/WB
32
32
5
2
32
1
32
5
107
32
5
103
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Consider this sequence:
sub
and
or
add
sw
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$2, $1,$3
$12,$2,$5
$13,$6,$2
$14,$2,$2
$15,100($2)
We can resolve hazards with forwarding
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§4.7 Data Hazards: Forwarding vs. Stalling
Data Hazards in ALU Instructions
How do we detect when to forward?
Chapter 4 — The Processor — 24
Dependencies & Forwarding
Chapter 4 — The Processor — 25
Detecting the Need to Forward

Pass register numbers along pipeline
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ALU operand register numbers in EX stage
are given by
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e.g., ID/EX.RegisterRs = register number for Rs
sitting in ID/EX pipeline register
ID/EX.RegisterRs, ID/EX.RegisterRt
Data hazards when
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
Fwd from
EX/MEM
pipeline reg
Fwd from
MEM/WB
pipeline reg
Chapter 4 — The Processor — 26
Detecting the Need to Forward
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But only if forwarding instruction will write
to a register!
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EX/MEM.RegWrite, MEM/WB.RegWrite
And only if Rd for that instruction is not
$zero
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EX/MEM.RegisterRd ≠ 0,
MEM/WB.RegisterRd ≠ 0
Chapter 4 — The Processor — 27
Forwarding Paths
Chapter 4 — The Processor — 28
Forwarding Conditions
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EX hazard
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if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
ForwardA = 10 #Two bit control signal to MUX
if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt))
ForwardB = 10
MEM hazard


if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01
Chapter 4 — The Processor — 29
Double Data Hazard

Consider the sequence:
add $1,$1,$2
add $1,$1,$3
add $1,$1,$4
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Both hazards occur
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Want to use the most recent
Revise MEM hazard condition
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Only fwd if EX hazard condition isn’t true
Chapter 4 — The Processor — 30
Revised Forwarding Condition
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MEM hazard
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if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt))
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01
Chapter 4 — The Processor — 31
Datapath with Forwarding
Chapter 4 — The Processor — 32
Load-Use Data Hazard
Need to stall
for one cycle
Chapter 4 — The Processor — 33
Load-Use Hazard Detection
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Check when using instruction is decoded
in ID stage
ALU operand register numbers in ID stage
are given by
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Load-use hazard when
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IF/ID.RegisterRs, IF/ID.RegisterRt
ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or
(ID/EX.RegisterRt = IF/ID.RegisterRt))
If detected, stall and insert bubble
Chapter 4 — The Processor — 34
How to Stall the Pipeline

Force control values in ID/EX register
to 0
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EX, MEM and WB do nop (no-operation)
Prevent update of PC and IF/ID register
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Using instruction is decoded again
Following instruction is fetched again
1-cycle stall allows MEM to read data for lw
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Can subsequently forward to EX stage
Chapter 4 — The Processor — 35
Stall/Bubble in the Pipeline
Stall inserted
here
Chapter 4 — The Processor — 36
Stalls and Performance
The BIG Picture
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Stalls reduce performance
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But are required to get correct results
Compiler can arrange code to avoid
hazards and stalls
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Requires knowledge of the pipeline structure
Chapter 4 — The Processor — 37