Transcript SATA技术简介

SATA
(SATA 1.0a, PHY & LINK Layer)
SATA 1.0a, PHY & LINK Layer
Overview
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Background
PHY
Link Layer
Transfer Layer
IP
Appendix
SATA Stadard
SATA Standard evolution
SATA 2.6
SATA 2.5
SATA 1.0a
bug fixed
SATA 1.0
SATA 2.0
1.8” disk micro SATA
mini SATA multi-channel cable
and IF
SATA transmission speed
Generation-1
SATA 150MBps(1.5Gbps)
Generation-2
SATA 300MBps(3.0Gbps)
Generation-3
SATA 600MBps(6.0Gbps)
Note: SATA using 8bit/10bit encode for data transmission,
son the Bps can be converted to bps by X10
(SATA 1.0,
SATA 1.0a)
(SATA 1.0,
SATA 1.0a,
SATA 2.0)
ATA System Model
Share one cable between
mast and slave disk
SATA system model
same as ATA
Different from ATA
• One cable per hard disk (no
mast/slave disk)
• transparent to upper layer
software(upper layer software
operating ATA hard disk)
SATA Layered control model
Driver software
Controller
Hardware
SATA host
communication
and FSM control
Serial data Tx/Rx
and FSM control
Overview
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Background
PHY Layer
Link Layer
IP
Appendix
PHY hardware requirement
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1.5Gbps,Differential NRZ
100 Ohm matching resistor Tx/Rx
Serial-parallel/Parallel-Serial conversion
Out of band signal detection
Speed negotiation
Hardware status detection and report
Allow for small data rate variation for spectrum
spread
+0/-0.5% , variation period is 33.33us
• Support cooperated synchronization
SATA Socket
Power
Signal (7 wire)
SATA Signal connection
SATA host
controller
SATA
cable
SATA
device
controller
Signal Voltage(DC couppled)
+500mV
250mV
0mV
0
1
idle
Tx PHY
Rx PHY
Detect
special
control
signal
Example of Tx circuits
Overviee
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Background
PHY Layer
Link Layer
Transfer Layer
IP
Appendix
Link Layer
Function
– Tx/Rx data frame
– Tx/Rx Speed Synchronization
– Coding and error detection
Initialization
OOB (Out of Band) Command
• Periodical ALIGN signal
Initialization
（OOB
Command )
Detection
circuits
Frame structure
…
Data Frame
Data
Frame
…
primitive
Data
primitive and Data format
primitive
Consists of 4
coding segment
each coding
segment
consists of 10-bit
Each 10-bit code is converted
from original 8-bit code
Data
8b/10b Encoding (Implementation Example)
Running
Disparity
bit
DFF
8-bit original code
Type（D/K）
D for data
K for control
Combinatorial Logic
Circuits
10-bit encoding
result
8b/10b Code table
primitive
primitive
first transmitted
bit
last transmitted
bit
primitive data
primitive data
primitive data
primitive flag
Primitive
primitive
Tag
Mean
ALIGN
Synchronization(used for PHY layer, invisible to link layer)
CONT
Repeat last primitive (for EMI)
DMAT
Receiver request for stop (transfer)
HOLD
Transfer pause(no enough data to send or not enough
buffer to receive)
HOLDA
Response to HOLD command
PMREQ_P
Power management(power saving)request
PMREQ_S
Power management(sleep)request
PMACK
Accept power management request
PMNAK
Reject power manage request
R_RDY
Receiver side ready
X_RDY
Transmit side ready
R_ERR
Receive error
R_IP
Receive in progress
R_OK
Receive OK
SOF
Start of frame
EOF
End of frame
WTRM
Wait for response from receiver after sending one frame
SYNC
Synchronization
primitive DMAT
(Host send data to Device)
HOST send data to Device
SATA
Host
Device send DMAT to Host
SATA
Device
When device ask for stop，Host stop data transfer, but
keep internal state, so that the data transmission can be
restarted
primitive DMAT (Device sent data to
Host)
Device send data to Host
SATA
Host
Host send DMAT to Device
SATA
Device
When Host ask for stop, Device stop transmission, but
not keep internal state, transmission cannot be
recovered
primitive CONT
…
primit primit
CONT
ive A ive A
repeat twice
before send
CONT
Ana data
Any data is regarded as
the repeating primitive
A
Reduce spectrum peak
primit
ive B
…
primitive
repetition
stopped after
receiver a new
primitive B
Flow control
• HOLD
• HOLDA
SOF
HOLDA
Data
…
response
delay
Sender
…
R_RDY R_IP
CONT
Useles
s data HOLD
receiver
Structure of data frame
start of
frame
data
type
FIS
SOF
Type
data
FIS Contents
end of
checksum frame
CRC
EOF
Note
• CRC is on original data (before 8b/10b conversion)
• G(X)=x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1
• The transmitted data require further scrambling
Generation of transmitting data
data before
8b/10b
conversion
FIS
Type
32-bit
CRC calculation
FIS
32-bit
32-bit
32-bit
32-bit
data before
8b/10b
conversion
32-bit
CRC
8bit/10bit Conversion
data after
8b/10bco
nversion
FIS
Type
40-bit
40-bit
40-bit
40-bit
40-bit
40-bit
LFSR (G(x)=x16+x15+x14+x13+x4+x1)
scrambling
SOF
CRC
FIS Contents
FIS Type
FIS Contents
CRC
EOF
Overview
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Background
PHY Layer
Link Layer
Transfer Layer
IP
Appendix
Data seen from different layer
ATA registers
and status
Application
Layer
Transfer
Layer
data before
8b/10b
conversion
FIS
Type
32-bit
CRC Calculation
FIS
32-bit
32-bit
32-bit
32-bit
32-bit
CRC
8bit/10bit conversion circuits
Link Layer
data after
8b/10b
conversion
FIS
Type
40-bit
SOF
40-bit
40-bit
40-bit
40-bit
40-bit
LFSR电路 (G(x)=x16+x15+x14+x13+x4+x1)
scrambling
Physical
Layer
CRC
FIS Contents
FIS Type
FIS Contents
CRC
EOF
Transfer Layer
ATA data /control registers
Transfer layer is a
interperator
FIS
Type
FIS
data frame (FIS)
Data structure seen by the transfer layer
(Example)
Thanks