Transcript Lehman Review, June 2000

D
The DØ Silicon Microstrip Tracker
Frank Filthaut
University of Nijmegen / NIKHEF
NIKHEF, 4 August 2000
D
Tevatron Run II Upgrade
Modification of Tevatron parameters:
Run 1
Run 2
(initial)
Run 2
(eventual)
Bunch spacing
(ns)
3500
396
132
Luminosity
(1031 cm-2 s-1)
0.16
8.6
21
Interactions/
crossing
2.5
2.3
1.9
Start of Run II: 1 March 2001
Aim: collect 2 fb-1 in  two years (might be more…)
Switch from 396 ns to 132 ns bunch spacing at
luminosity  1032 cm-2 s-1
Keep zero crossing angle for 396 ns operation; aim
for 136 rad angle for 132 ns operation
Beam spot:  35 m transverse, 25 cm longitudinal
(10 cm for nonzero crossing angle)
NIKHEF
4 August 2000
D
DØ Run II Upgrade
 Addition of central axial 2T magnetic field (SC




solenoid in front of calorimeter cryostat)
Replacement of tracking system by combination of
scintillating fibers (Central Fiber Tracker) and silicon
sensors (Silicon Microstrip Tracker)
Central (CPS) and forward (FPS) preshower detectors
Extend muon chamber coverage to larger , smaller
granularity
Upgraded calorimeter, trigger, DAQ electronics
Physics aims:
 B-tagging based on b lifetime
 Improved electron and muon identification and
triggering
 Improved tau identification
 Charge sign determination

High pt central physics (tt, EW, Higgs and other
searches): high multiplicity
 QCD): requires good forward
Low p physics (bb,
t
coverage (e.g. lepton ID for || < 3)
NIKHEF
4 August 2000
D
DØ Run II Upgrade
NIKHEF
4 August 2000
D
DØ Run II Upgrade - Tracking
Silicon Microstrip Tracker
Fiber Tracker
Forward
Preshower
Solenoid
Central Preshower
All share the same SVX IIe front-end electronics
NIKHEF
4 August 2000
D
SMT Design
Basic SMT Design:
 6 barrels
 12 F disks
 4 H disks
1112
10
9
34
2
1
2
1
3
6
4 5
7 8
5 6
Totals: 793k channels
3.0 m2 (of which 1.6 m2 DS)
Layers/planes
Readout
Length
Inner Radius
Outer Radius
Barrels
4
12.4 cm
F-Disks
12
7.5 cm
H-Disks
4
14.6 cm
2.7 cm
9.4 cm
2.6 cm
10.5 cm
9.5 cm
26 cm
Axial strips to be used in 2nd level Silicon
Track Trigger (STT)
 stringent requirements on alignment
NIKHEF
4 August 2000
D
SMT Design
SMT barrel cross-section:
 Layers 1 (3): 12 (24) DS, DM 900 ladders produced
from 6” wafers
(barrels 1 & 6: SS axial ladders from 4” wafers)
 Layers 2 (4): 12 (24) DS 20 ladders produced from 4”
wafers
Ladder count: 72 SS + 144 DS (900) + 216 DS (20)
NIKHEF
4 August 2000
D
Anatomy of a Ladder
 Ladders supported by “active” (cooled) and “passive”
bulkheads
 Ladders fixed by engaging precision notches in
beryllium substrates on posts on bulkheads
 Beryllium cools electronics


expect chips to operate at 25 0C using
80% H2O/20% ethyl glycol mixture at –10 0C
silicon should be at 5-10 0C
 High Density Interconnect (HDI) tail routed out
between outer layers
 Carbon-fibre/Rohacell rails glued to sensors for
structural stiffness
NIKHEF
4 August 2000
D
Silicon
Calculated radiation dose as a function of radius (z=0):
T itle:
radf_bas e.eps
Creator:
HIGZ Versi on 1.22/09
Preview:
T his EPS pic ture was not s aved
with a preview i nc luded i n i t.
Comment:
T his EPS pic ture wi ll pri nt to a
Pos tScri pt printer, but not to
other types of printers.
 Significant fraction of
silicon will undergo type
inversion
 Prefer high initial Vdepl
for silicon at low radii


Specification of Vdepl,
Vbreak
Selection of sensors at
hand
Quality control at vendors & DØ institutes:
 Ileak < 10 A at Vbias = Vdepl + 10V
 20V < Vdepl < 60V
 Polysilicon bias resistors: 1 M < Rbias < 10 M
(DC bias pad)
 Rinter-strip  G
 Coupling capacitors: 10-15 pF/cm
 f(shorted cap’s) < 2% at min(Vdepl+15V, 90V)
NIKHEF
4 August 2000
D
Sensors
Single-sided
 Need 144 sensors




NIKHEF
(2/detector)
Pitch: 50 m
Typical Vdepl: 30 V
All sensors delivered
by Micron
Flatness problems
( 60 m) a concern
4 August 2000
D
Sensors
Double-sided 20
 Need 432 sensors (2/detector)
 Pitch: p-side 50 m, n-side 62.5 m
 Typical Vdepl: 20-40 V
 Slow sensor delivery by Micron
 accepting sensors with higher Rbias
p-side
NIKHEF
n-side
4 August 2000
D
Sensors
Double-sided, double-metal
 Need 144 sensors
 Pitch: p-side 50 m, 900 n-side 153 m
 Produced from single sensor (6” technology)
 Using DM layer, gang 2 n-side strips together to
form 1 readout channel
 Typical Vdepl: 50 V
NIKHEF
4 August 2000
D
Sensors
Double-sided, double-metal
 Sensor delivery from Micron has been slow (30%
yield) mainly due to p-stop defects on mask (noise
affecting  10-15 strips)
  5 sensors / week
 schedule problem, accepting few sensors with
1 p-stop defect
NIKHEF
4 August 2000
D
Sensors
F-wedge
 Need 144 sensors (12 detectors/disk)
 Pitch: n-side 62.5 m, p-side 50 m
(flexible pitch adaptor on n-side)
 Stereo angles: 150
 Sensor delivery:


NIKHEF
Micron: delivered 125 sensors with reasonable
characteristics: Vdepl  60-70 V
Eurisys: delivered 65 sensors:
 First two batches: Vdepl  15-20 V, Vbreak  70-80 V
 Last batch ( 25 sensors) with better implants:
Vdepl  30-40 V, Vbreak  80-100 V
4 August 2000
D
Sensors
H-wedge
 Need 384 sensors (2/detector, 48 detectors/disk)
 Single-sided, glued back-to-back
 Pitch: 80 m
 Stereo angles: 7.50
 Typical Vdepl: 60 V
 All sensors delivered by ELMA
NIKHEF
4 August 2000
D
SVX IIe Chip
 SVX chip originally designed by LBL - FNAL for







NIKHEF
readout of CDF vertex detector, optimised for
capacitances of 10-35 pF, ENC = 350e- + 50e-/pF
128-channel 8-bit digital chip, 1.2 m rad-hard
technology
Both signal polarities
Rise time set to integrate 99% of signal in 100 ns
(for 132 ns operation)
Double correlated sampling for dynamic “pedestal”
subtraction
Front end capacitor discharged during “beam gaps”
Pipeline depth 32 max.
106 MHz readout speed (both edges of 53 MHz clock)
4 August 2000
D
SVX IIe Chip
 Daisy-chained readout of max. 9 chips
 Online sparsification using common threshold. Modes:
 All channels
 Only above threshold
 Include 1 or 2 neighbours on either side (even if on
adjacent chips)
 Adjustable ramp rate (dynamic range)
 Power dissipation  5 mW/channel
 Unlike SVX III now in use by CDF, not deadtime-less
NIKHEF
4 August 2000
D
High Density Interconnect
Need 912 HDI’s
 Two-layer flex-circuit mounted directly on silicon,
housing SVX chips as well as passive electronics
 Kapton based, trace pitch 200 m
 Connects to “low-mass” cable using Hirose connector
 9 different types for the 5 sensor types


2 for each sensor type except H disks
2 types for each ladder differ only in tail length
 Laminated to beryllium substrate
(total mass  0.041 X0, of which 0.014 X0 from Si)
9-chip HDI
NIKHEF
H-wedge HDI
4 August 2000
D
Production Sequence
Silicon
Sensors
Micron
Eurisys
ELMA
HDI
Probe Test
Silicon Sensor
at Micron
Test Bare HDI
Laminate HDI
Mount
components
HDI
Probe Test
Silicon Sensor in
house
Promex
on
Test stuffed HDI
Burn-in HDI
Build Ladder/Wedge
Mount HDI on Silicon
Wirebond Detector
Burn-in Ladder
Laser Test
Outside Co.
University
Build Full Wedge (H)
Mount on Support
structure
Read out Detector
Fermilab
NIKHEF
Dyconex
4 August 2000
“fail”
Silitronics
“fail”
Ladder Production in steps (9-chip)
D
1. Apply pattern of
non-conductive
epoxy on p-side
beryllium
2. Align beryllium with
respect to active sensor,
apply pressure and cure
for 24 hr
3. Align active & passive
sensors w.r.t. each other,
apply wirebonds.
Then use separate fixture
to position carbon-fibre
rails. Use conductive epoxy
to ground “passive”
beryllium. Cure for 24 hr
NIKHEF
4 August 2000
Ladder Production in steps (9-chip)
D
4. Use “flip fixture”
to have n-side on top
5. Apply epoxy to n-side
beryllium, fold over and
secure HDI. Apply
pressure and cure for
24 hr.
Then apply n-side Si-Si
and Si-SVX wirebonds
6. Encapsulate bonds at
HDI edges.
Connect “active”
beryllium to cable ground
NIKHEF
4 August 2000
D
Testing & Repairs
 Broken capacitors: cause SVX front-end to saturate,
tends to affect neighbouring channels as well
 pluck corresponding bonds
 Bad grounding of beryllium substrates causes large
pedestal structures as well as high noise
 ensure RBe-gnd < 10
 Repair broken / wrong bonds
 Replace chips / repair tails damaged during processing
250
mean
noise x10
200
diff. noise x-1
150
100
50
0
-50
0
128
256
384
512
640
768
896
1024 1152
Bonds need to be plucked
Bad ground connection
NIKHEF
4 August 2000
D
Burn-in & Laser Tests
Burn-in Test:
Long-term (72 hr, 30’ between runs) test of whole
ladder/wedge (conditions close to those in experiment)
Laser Test:
 Energy just < Si bandgap
(atten. length  400 m
 test whole sensor)
 Find dead & noisy channels
 Determine initial operating
voltages (from pulse height
plateau, Ileak-V curve)
256
pulse height
192
Laser
128
64
0
0
128
256
Dead Channel
NIKHEF
4 August 2000
384
x-y movable
laser head
D
Overall Quality (first half-cylinder)
Detector classification:
 Dead channel: laser response < 40 ADC counts
 Noisy channel: pedestal width > 6 ADC counts
(normally < 2 counts excluding coherent noise)
 Grade A: less than 2.6% dead/noisy channels
 Grade B: less than 5.2% dead/noisy channels
Use only detector grades A,B; mechanically OK
Example for 9-chip detectors:
Dead
T itle:
c hip9_pn_dead.eps
Creator:
HIGZ Versi on 1.25/05
Preview:
T his EPS pic ture was not s aved
with a preview i nc luded i n i t.
Comment:
T his EPS pic ture wi ll pri nt to a
Pos tScri pt print er, but not t o
other t ypes of printers.
Noisy
T itle:
c hip9_pn_noise.eps
Creator:
HIGZ Versi on 1.25/05
Preview:
T his EPS pic ture was not s aved
with a preview i nc luded i n i t.
Comment:
T his EPS pic ture wi ll pri nt to a
Pos tScri pt print er, but not t o
other t ypes of printers.
(better for other detector types)
NIKHEF
4 August 2000
D
Production Status and Projection
(as of July 7)
9 Chip
3 chip
6 Chip
1
Yield Folded Detector Production
H disk
F Disk
Nov 1, 00
Fraction Complete
0.8
Aug 10, 00
0.6
50% line
0.4
July 7
0.2
0
31-Mar-99
9-Jul-99
17-Oct-99
 Projected rates:




9-chip: 9.0/week
6-chip: 5.4/week
H-wedge: 6.2 week
F-wedge: 4.3/week
25-Jan-00
4-May-00
12-Aug-00
20-Nov-00
Date
assumed yield
80%
85%
85%
90%
capacity
15/wk
10/wk
10/wk
15/wk
Rates include production, but in general dominated by
sensor delivery.
However, HDI “stuffing” at Promex (9-chip) also a
concern
(wire bond pull strength, HDI bubbling during surface mount)
NIKHEF
4 August 2000
Barrel Assembly in steps
D
 Rule of thumb:

Align to 20 m (trigger)
Survey to 5 m (offline)
 Precisely machined bulkheads
 Barrel assembly done inside out (protect wire bonds)

1. Insert individual
ladders into rotating
fixture using 3D
movable table
2. Manually push
notches against posts
(all under CMM)
NIKHEF
4 August 2000
D
Barrel Assembly
 Layer 4 glued to bulkheads (providing structural
stiffness, holding passive BH)
 Thermally conductive grease applied (active BH only)
for other layers
3. Secure ladder
using tapered pins
First 3 barrels
assembled
( 4 weeks/barrel,
excluding survey)
NIKHEF
4 August 2000
D
Barrel Alignment
Results for first barrel (similar for other two):
Note: relevant quantities are distributions’ RMS values
(trigger accounts for average offsets)
 Shift d across ladder (3 m)
 Shift  in radius (from ladder

flatness, better than 60 m)

 Rotation  in ladder plane
(10 m  3 m)
 Rotation  about short ladder axis
(70 m  4.6 m)
 Rotation  about long ladder axis
(80 m  3.2 m)
Example: distribution for :

Should be OK for trigger purposes
NIKHEF
4 August 2000


D
F-Disk Assembly
 F-disk assembly less critical (not included in trigger),
nevertheless performed under CMM
 Quick process
 After assembly, “central” F-disk cooling rings screwed
onto active barrel bulkheads
Distribution of different quality devices over disks:
z=0
Vdepl H H L
H
L
M
M
L
H
L HH
H/M = Micron high/medium Vdepl, L = Eurisys low Vdepl
NIKHEF
4 August 2000
D
Support Cylinder
 Double-walled carbon fibre structure supporting all
but H disks (supported by CFT layer 3)
 Split support (cut at z=0) introduced very late: gain
6 months of “schedule time” (installation can be done
with end-cap calorimeter cryostats on platform)
 First half-cylinder ready
NIKHEF
4 August 2000
D
Readout Electronics
Monitoring
Control
HDI
3M
Low Mass
IB
S
E
Q
Optical Link
1Gb/s
NRZ/
CLK
VME
68k
S
E
Q
S
E
Q
platform
V R B
V
B
D
1
5
5
3
VRB
Controller
L3
Secondary
Datapath
HOST
Examine
 For 5% occupancy, 1 kHz trigger rate: 1010 bits/s
 need error rate  10-15
 Exercise readout system as much as possible before
installation in experiment
 10% system test using full readout chain
(readout full F disk, barrel, barrel-disk assembly, H disk)
 Complete readout chain (including L3 analysis, data
storage) tested on several detectors
NIKHEF
4 August 2000
D
Schedule
Milestone
Barrel
Barrel
Barrel
Barrel
Barrel
Barrel
1 Complete
2 Complete
3 Complete
4 Complete
5 Complete
6 Complete
F
F
F
F
F
F
F
Disk
Disk
Disk
Disk
Disk
Disk
Disk
0 Complete
1 Complete
2 Complete
3 Complete
4 Complete
5 Complete
6 Complete
F
F
F
F
F
F
Disk
Disk
Disk
Disk
Disk
Disk
7 Complete
8 Complete
9 Complete
10 Complete
11 Complete
12 Complete
H Disk
H Disk
H Disk
H Disk
1 Complete
2 Complete
3 Complete
4 Complete
Finish Date
April 18,
May 23,
June 28,
July 27,
August 24,
September 22,
Done
Done
Done
In preparation
Done
Done
Done
Done
Done
Done
Done
Started
Started
March 28,
April 11,
April 25,
May 9,
May 23,
June 21,
July 6,
2000
2000
2000
2000
2000
2000
July 20,
August 3,
August 17,
August 31,
September 15,
October 6,
2000
2000
2000
2000
2000
2000
May 17,
July 7,
August 25,
October 16,
2000
2000
2000
2000
4 August 2000
May 18, 2000
June 13, 2000
July 14, 2000
2000 March 31, 2000
2000 May 10, 2000
2000 May 23, 2000
2000 June 15, 2000
2000 June 30, 2000
2000
July 10, 2000
2000
July 19, 2000
South Half-Cylinder Complete and Ready to Move
Julyto
27,
DAB
2000
North Half-Cylinder Complete and Ready toOctober
Move to27,
DAB
2000
NIKHEF
Completed
Half done
Cost
NIKHEF
WBS
1.1.1
1.1.1.1
1.1.1.1.1
1.1.1.1.2
1.1.1.1.3
1.1.1.1.4
1.1.1.1.5
1.1.1.2
1.1.1.2.1
1.1.1.2.1.1
1.1.1.2.1.2
1.1.1.2.1.3
1.1.1.2.1.4
1.1.1.2.1.5
1.1.1.2.1.6
1.1.1.2.1.7
1.1.1.2.2
1.1.1.2.2.1
1.1.1.2.2.2
1.1.1.2.2.3
1.1.1.2.2.4
1.1.1.2.2.5
1.1.1.2.2.6
1.1.1.2.3
1.1.1.3
1.1.1.3.1
1.1.1.3.2
1.1.1.3.3
1.1.1.3.5
1.1.1.3.7
1.1.1.3.8
1.1.1.3.9
1.1.1.3.10
1.1.1.3.11
1.1.1.3.12
1.1.1.4
1.1.1.4.1
1.1.1.4.2
1.1.1.4.3
1.1.1.4.4
1.1.1.4.5
1.1.1.4.6
1.1.1.4.7
1.1.1.4.8
1.1.1.5
1.1.1.5.1
1.1.1.5.2
1.1.1.5.3
1.1.1.5.4
1.1.1.5.5
1.1.1.5.6
1.1.1.5.7
1.1.1.5.8
1.1.1.6
1.1.1.6.1
1.1.1.6.2
1.1.1.6.3
1.1.1.6.4
1.1.1.6.5
1.1.1.7
1.1.1.7.1
1.1.1.7.2
1.1.1.7.3
DESCRIPTION
SILICON TRACKER
Engineering & Design
SVX II engineering
MOSIS submission
UTMC submission
HDI engineering
Test readout system
Disks
F disk
F wedge detectors
F wedge berylium
Probe testing
F disk fixtures
F wedge fabrication
F Disk Support
F wedge det. spares
H disk
H wedge detectors
Probe testing
H wedge substrate
H disk fixtures
H wedge fabrication
H Disk Support
Spares
Barrels
Single Sided
Single Sided Spares
2 Degree
90 Degree
Probe Testing
Berylium substrates
Ladder Fixtures
Barrel assembly fixtures
Ladder fabrication
Bulkheads
Readout IC's
F disk
H disk
Layer 1
Layer 2
Layer 3
Layer 4
Chip testing
Spares
Readout System (Detector to Port Card)
Disk HDI
Barrel HDI
HDI assembly and test
Low Mass Cables
High Mass Cables
Transition Card
Bias Voltage System
Interface board
Mechanical Support, Services
Half-cylinder
Installation fixtures
Cooling system
Air system
Monitoring system
Detector Assembly, Installation
Silicon install fixturing
Silicon Supports
Installation services
4 August 2000
COST
EST
7,857,073
525,541
157,500
55,000
113,600
0
199,441
1,407,507
859,485
539,365
24,580
51,904
25,695
23,604
128,292
66,045
460,986
278,950
12,000
43,061
19,740
44,026
63,209
87,036
2,567,736
218,162
284,803
1,034,747
395,307
209,647
138,450
47,028
23,523
38,791
177,278
578,724
155,957
88,744
27,733
49,919
55,465
99,837
37,869
63,200
2,622,983
150,419
347,449
344,216
682,034
425,736
113,460
80,669
479,000
114,582
32,000
10,000
42,582
10,000
20,000
40,000
15,000
15,000
10,000
D