Transcript FinFET Introduction on 3T1D

FINFET INTRODUCTION ON
3T1D-DRAM CELL
E.Amat and A.Rubio
Main ideas/objectives
2
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



Simulate 3T1D-DRAM cell based on FinFET devices.
Observe its performance & possible improvements.
Analyze the variability influence.
Study the temperature relevance on cell behavior.
No reliability studies have been observed before
about the introduction of FinFET on 3T1D-DRAM.
Outline
3
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
Introduction
Experimental work
Results
 Device
characterization
 FinFET vs. Bulk
 Temperature

Conclusions
Introduction
FinFET (I)
Experimental
Results
Conclusions
4
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Important candidates to substitute CMOS devices.
 Good
short channel effects control.
 Quasi-planar implementation.
 Low channel doping.

Reduction of process variation influence.
 Work

function (WKF) main source on variability.
FinFET based on Bulk or SOI technology.
 SOI
higher wafer cost & defect density. (IBM)
 Bulk more complex and difficult variability control. (Intel)
 Higher
and optimized doping is required.
Introduction
FinFET (II)
Experimental
Results
Conclusions
5
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Different configurations:
IG-FinFET
 Shorted-gate
(SG): Higher Ion, 3-terminals…
 Double-gate (DG): VT control, 4-terminals…
 Modify
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charge density and its distribution.
Shrink device dimensions till 10nm & beyond.
Better performance at low VDD.
Mix bulk and FinFET in a same circuit is possible.
Drawback: self-heating, worst Temp. performance.
Introduction
FinFET & 3T1D-DRAM cells
Experimental
Results
Conclusions
6

3T1D promising candidate to substitute 6T-SRAM.
 Larger
density, similar velocity, lower variation impact…
 T1’s variability has strong influence on cell performance.
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FinFET introduction allows new
cell configurations [Bohj’10].
No work have deeply studied.
Introduction
Samples and simulations
Experimental
Results
Conclusions
7
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Samples used at VDD=1
 FinFET
SOI models: PTM (32nm) and TRAMS (10nm)
 Bulk devices: PTM (32nm)

Cell parameters:
Write Access Time(WAT): V(WLw)=VDD/2 & V(S)=0.9*(VDD-VT)
 Read Access Time(RAT): V(WLr)=VDD/2 & V(BLr)=0.9*VDD
 Power consumption(PW) average on a cycle.
 Retention Time(RT): V(S)=0.9*(VDD-VT) & V(S)=VT,T2/AF


Temperature influence 60, 100 and 125ºC.
Introduction
Experimental
Cell variability
Results
Conclusions
8
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10.000 Monte Carlos simulations.
Usually, FinFET shows ~half variability impact.
Variability
Moderate
High
Bulk (32)
6%
15%
FinFET (32)
3%
7%
TRAMS model process variation is stated at:
 41.2mV
or 51.3mV in function of MGG of 5 or 10nm.
 When all the variability sources are combined.


Minimum device dimensions (Pelgrom).
Variability (%) = 3σ/µ
Introduction
Experimental
Device characterization
Results
Conclusions
9
DG & SG are compared
 SG:
higher ION
 DG: Back gate govern a VT-shift
abs (ID) (A/µm)

-3
10
 Low
leakage, stepper sub-threshold
swing slope.
FinFET
DG32 (VBG ± 0.3)
FinFET
DG32
± 0.3)
SG32 (VFG
BG=V
BG)
SG32
(V
=V
SG10 FG BG)
Bulk SG10
32nm
-6
10
-8
0.0
0.0
10
10
ION / IOFF
 Higher ION.
-5
10
10
shows higher ION/IOFF
FinFET vs. Bulk (32nm):
-0.3
-7
lower VT & minimize leakage.
 Improve ION/IOFF

-4
10
10
 ~-0.3V,
 10nm
0.3
0.3
10
10
10
0.2
0.2
0.4
0.6
VFG
(V)
FG
0.8
5
4
3
2
1
DG32
SG32
SG10
bulk32
ION (VG=VD=0.9V)
IOFF (VG=0 & VD=0.9V)
-0.2
0.0
VBG (V)
0.2
Introduction
3T1D FinFET performance (I)
Experimental
Results
Conclusions
10

Several 3T1D configurations:
 Type
3 ‘classical’ presents the best
performance.
3T1D
WAT (ps)
RAT (ps)
PW (µW)
RT (µs)
T3
393.1
14.8
1.3
1.4
T4
1847.2
12.4
1.4
1.2
T5
1335.8
480.2
10.3
1.3
T6
368.3
15
1.4
1.2
Introduction
Experimental
3T1D FinFET performance (II)
Results
Conclusions
11
T1 determines cell performance.

Correct cell behavior is observed.
DG configuration shows mismatching for VBG,T1>0.
 While VBG,T1<0 depicts good performance.

7
10
FinFET 32nm
SG (VFG = VBG)
DG (VBG,T1 = ±0.3)
1.5
-5
6
10
-6
-7
5
3T1D-DRAM cell
T1
T2
T3
D1
4
10
10
1.0
WAT (ps)
10
-0.3
VS (V)
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For us, RT is the main parameter.
RT (s)

0.5
0.3
-8
-9
full: RT
open: WAT
-0.2
0.0
VBG (V)
0.0
2
3x10
0.2
0
20
40
60
time (ns)
80
Introduction
Experimental
DG-FinFET vs Bulk
Results
Conclusions
12
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3T1D-DRAM based on FinFEt or Bulk (32nm).
SG-FinFET is the faster cell.
DG-FinFET presents the best performance.
 Faster
cell
 Highest RT
WLread
WLwrite
1400
32nm
WAT 50
RT
1200
T3
S node
BLwrite
40
T1
1000
30
800
20
600
10
400
Bulk
DG-FinFET
SG-FinFET
RT (µs)
WAT (ns)

-0.3V
WLread
D1
T2
BLread
Introduction
Experimental
RT improvement
Results
Conclusions
13
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RT stated as reference parameter.
Small RT is obtained for SG (~2µs).
 High

leakage currents
VBG,T1 <0 presents relevant RT enlargement (~50µs).
 Lower
leakage currents
100
700
600
500
1
0.01
0.001
I (pA)
RT (µs)
10
0.1
SG-FinFET 32nm
ID,T1
abs (IG,D1)
abs (IG,T2)
FinFET
SG 32nm
SG 45nm
DG 32nm
DG 45nm
-0.2
0.0
VBG,T1 (V)
400
DG-FinFET 32nm
VBG,T1 = -0.3V
ID,T1
abs (IG,D1)
abs (IG,T2)
20
15
I (pA)

10
300
200
5
100
0.2
0.0
0.4
0.8
time (µs)
1.2
0
10
20
30
40
time (µs)
50
Introduction
Experimental
3T1D variability
Results
Conclusions
14
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DG-FinFET has shown the best behavior in RT terms.
Moreover, lower variability has also observed.
 -0.3
offers the best relation
 Leakage
 VBG,T1
helps to reduce cell variability.
DG - FinFET SG – FinFET
Bulk
Mod
High
Mod
High
Mod
High
WAT
1.7
3.6
2.8
6.6
1.6
5.8
RAT
0.8
2.1
0.8
2.2
4.5
12.1
PW
0.2
0.4
0.4
0.5
0.8
2.6
RT
13.4
31.6
28.1
74
19.1
39.9
PTM 32nm
High var 7%
50
45
40
40
30
20
35
10
30
0
-0.30
-0.20
-0.10
VBG,T1 (V)
0.00
µ - RT (µs)
Variability
(%)
current reduction.
RT variability (%)

Introduction
Experimental
Low VDD performance
Results
Conclusions
15
At lower VDD:
 FinFET
shows good performance.
 VDD=0.8V
similar WAT values than Bulk with VDD=1V
 Relevant larger RT.
 Bulk
shows larger WAT-shift.
line: WAT
dash: RT
3500
50
3000
32nm
FinFET
Bulk
2500
40
30
2000
20
1500
WAT
RT
10
1000
500
0.6
0.7
0.8
VDD (V)
0.9
1.0
RT (µs)
Smaller VDD
WAT (ps)

Introduction
Experimental
Temperature influence
Results
Conclusions
16
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Temperature always is a detrimental factor
VSmin has a T-dependence that affects Ileakage.
FinFEt vs Bulk based on 32nm.
 FinFET:
impact, large µ reduction.
 Variability “control”.
 Bulk:
 Relevant
variability enlargement
 µ slight reduction.

DG
SG
bulk
140
120
50
40
30
100
green: TR. MGG10
blue: TR. MGG5
red: 32nm
80
60
20
10
40
0
40
60
80
100
Temperature (ºC)
TRAMS (10nm) model shows large variability.
120
µ - RT(µs)
 high
line: variability
dash: µ
160
RT variability (%)

Introduction
Experimental
2kB memory block
Results
Conclusions
17
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RT of 714ns ensures an IPC loss ~2%
 When
2kB DG-FinFET memory block shows better behavior.
 Even
at high Temp DG-FinFET block fulfill the limit.
1.00
1.00
High Variation
Bulk 15%
FinFET 7%
0.95
Yield
0.95
Yield
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comparing with an ideal 6T design.
0.90
714ns
0.85
High var.
FinFET 7%
0.90
Bulk
2kB block
DG-FinFET
25º
60º
100º
714ns
cell
2kB
FinFET
DG - cell
DG - 2kB
0.85
0.80
0.80
0
10
20
RT (µs)
30
40
0
5
10
RT (µs)
15
Introduction
Experimental
Conclusions
Results
Conclusions
18
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
Good behavior of a 3T1D-DRAM cell based on
FinFET at room temperature.
T1 shows again large influence on 3T1D cell
performance
 VBG,T1~-0.3V
revels the best results, due to lower
Ileakage.

DG-FinFET has presented a relevant improvement
on 3T1D-DRAM performance, higher RT.
 FinFET
VBG,T1 helps to control/mitigate leakage.
Introduction
Conclusions (II)
Experimental
Results
Conclusions
19
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Acceptable results at low VDD (~0.8V).
FinFET based cell presents better variability tolerance.
2kB 3T1D-DRAM DG-FinFET memory block presents
good performance.

With a IPC loss of 2%

Temperature reduces 3T1D-DRAM FinFET performance.

But even at 100ºC a 2kB memory block fulfill our RT criteria.