Transcript CMOS in the New Millennium - CUHK Electronic Engineering

SOI BiCMOS
 an Emerging Mixed-Signal
Technology Platform
Tak H. Ning
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Outline
• Evolution of Silicon Technology
• CMOS for Mixed Signal -- Why and Why
Not?
• Why SOI BiCMOS for Mixed Signal?
• Some Recent Developments
• Summary
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Evolution of Silicon Technology
CMOS + ?
CMOS
BiCMOS
PMOS/NMOS
BIPOLAR
1950 1960 1970 1980 1990 2000
CMOS
First
invented
bipolar
First
transistor MOSFET (1963)
(1947)
(1960)
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What Happened to BiCMOS?
• Previous BiCMOS aimed primarily for
digital applications
– CMOS was low power but very slow
– Digital BiCMOS goal was to add bipolar to
speed up CMOS circuits
– PENTIUM 1 was BiCMOS!
• CMOS speed improved by scaling
– Need for digital BiCMOS disappeared by
early 1990’s
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Devices Capable of e-Commerce Worldwide
Technology required:
computing + communication
Millions of devices
1400
1200
1000
800
600
Interactive Set-Top-Box
Mobile Handset
PC
400
200
0
1997
1998
1999
2000
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2002
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2005
Source: Gartner Dataquest (November 2000 Estimates)
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High-Speed CMOS Trends
•
•
•
•
Power supply voltage ~ 1 V
Gate oxide thickness ~ 1 nm
Short channel length but high off current
Not suitable for many analog applications
gate
source
Channel
length
Gate oxide
drain
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Technology Drivers and Trends
• System needs
– Faster, smaller, lower power, more reliable
• It is a mixed-signal world!
– CMOS for computing
– For communication :
• RF and analog CMOS, if it can be done
• Silicon bipolar, if CMOS cannot do it
• Non-silicon only if unavoidable
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Analog Transistors
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Colecrunt
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Typical MOSFET
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B
E
Typical bipolar
Bipolar is preferred
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Why BiCMOS?
• Systems need
– CMOS for high density and low power
digital functions
– Bipolar for RF and analog functions
• Integration for better systems
– Faster, smaller, lower power, more reliable
• Status:
– ALL major semiconductor companies either
shipping or developing BiCMOS
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Why Not BiCMOS?
• Cost, Cost, and Cost
– Process complexity
– Need to evaluate cost versus benefit
• Circuit design challenges:
– CMOS voltages scale (up to a point)
– Bipolar voltages do not scale
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Why SOI BiCMOS?
• SOI CMOS is here; bipolar is needed
• Isolation
– Devices automatically isolated from one
another
– Reduced substrate-coupling noise
• Cost?
– SOI wafer cost adder
– Cost saving associated with isolation
• Opportunities for innovation
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Why SiGe-Base Bipolar?
SiGe-base
• A much better RF and
analog transistor
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B
n+
p+
p+
n
C
n+
– Higher current gain
– Larger Early voltage
– Smaller transit times
n+ subcollector
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Improvement Factor: (SiGe)/(Si)
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The Challenge of BiCMOS
Bipolar
B
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n+
p+
p+
n
MOSFET
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S
n+
n+ subcollector
D
~ 0.2 mm
~ 2 mm
• Buried layer thickness issue
• Isolation issue
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The Challenge of SOI BiCMOS
Bipolar
SOI CMOS
Buried oxide
subcollector
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SOI BiCMOS
SOI BiCMOS has been around
for years!
What’s new?
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SOI BiCMOS -- for Mainframes
• SOI for reducing soft-error rate
• No power/speed advantage for CMOS
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Source: Hitachi, 1992 IEDM
SOI BiCMOS -- for Mixed Signal
• SOI on high-resistivity substrate
• 1 mm Si; no SOI advantage for CMOS
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Source: Hitachi, IEEE TED, vol. 49, 2002
Bipolar Transistors: from Bulk to Thin SOI
B
p+
E
n+
n
E
C
p+
B
p+
n+
0.1mm
n+
n+
C
n
n+
buried oxide
n+ subcollector
Bulk
~ 2 mm
substrate of SOI
Thin SOI
• Fully depleted collector SOI bipolar
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Fully-Depleted-Collector SOI Bipolar
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• Electrons drift across depleted collector
region towards reachthrough
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Source: J. Cai et al., 2002 Symp. VLSI Technology
SOI Vs. Bulk SiGe Bipolar Device
C
E
B
Subcollector
Experiment SOI bipolar
IBM’s Production
SiGe Bipolar
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Measured I-V Characteristics
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IC (mA)
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12
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4
0
0
IB step 1nA
IB0=50pA
1
2
VCE (V)
3
4
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Measured Cutoff Frequency
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VCB=0V
50
40
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0
-6
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H21 (dB)
Cut-off Frequency (GHz)
70
10
5
-20dB/dec
0
1
10
100
frequency (GHz)
-5
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Collector Current (A)
-4
10
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What About Cost?
• Cost adder:
– SOI substrate
• Cost subtracters:
– No subcollector
– No epi
– No deep trench
• Must look at cost versus benefit
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Complementary BiCMOS
NPN
•
PNP
PMOS
NMOS
INDUCTOR
No SOI
• fT of npn = 25 GHz
• fT of pnp = 2.5 GHz
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Source: NEC, 1998 IEDM
SOI Complementary BiCMOS
pnp
E
B
C n+ p+ n+
p+ p p+
npn
E
B
p+ n+
n+ n
nMOS pMOS
G
C
n+
G
S n+ D D p+ S
n+ p n+ p+ n p+
buried oxide
substrate of SOI
• npn, pnp, and CMOS on same thin SOI
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Advantage of Complementary Bipolar
Source: Hitachi, IEEE TED, 1995
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Technology Performance
Summary
Mixed-Signal
SOI BiCMOS
CMOS
Time
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Summary
• Silicon technology evolution continues
at rapid pace
• CMOS development is rapidly reaching
its limits
• Opportunities around the corner of the
redbrick wall
• SOI BiCMOS likely to emerge as
preferred technology platform for
mixed-signal applications
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