Transcript Implementation of DSP Algorithm on SoC

Part A Presentation
Implementation of DSP Algorithm on SoC
Student : Einat Tevel
Supervisor : Isaschar Walter
Accompanying engineer : Emilia Burlak
The project is conducted with
cooperation of Rafael.
winter 2003/2004
Project Goals - Review
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Studying and investigating the architecture of System
on Programmable Chip (SoC).
Deciding on the Software/Hardware partition to be
implemented.
Implementing a signal processing algorithm on the
chosen platform.
First Semester:
• Full understanding of the elements and
studied environments.
• Writing and Running examples on the
evaluation board.
Project Schedule
Second Part of First Semester
Studying the PowerPC processor.
Studying the EDK software for developing SoC.
Studying the SoC design process.
Get familiar with the Xilinx’s evaluation board.
Writing and Running examples on the evaluation
board.
System View
FPGA
Block
RAM
FPGA
Block
RAM
PowerPC 405
Core
I-Cache
D-Cache
CoreConnect On-Chip Peripheral Bus (OPB)
PLB-OPB
Bridge
Low Speed
Peripherals
CoreConnect Processor Local Bus (PLB)
User
Logic
External
Memory
High Speed
Peripherals
Implementation Tools
EDK - Embedded Development Kit
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Provides a set of design tools and a wide selection of standard
peripherals required to build embedded processor systems.
XPS (Xilinx Platform Studio) – Provides an integrated environment
for creating the software and hardware specification flows.
Standard peripherals (GPIO, SDRAM, Clock Modules, Ethernet).
GNU based software tools (C compiler, assembler, linker and
debugger) .
Virtex-II Pro FF1152 Development Board
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Enables implementation of embedded processor based applications
using IP cores and customized modules.
Virtex II Pro FPGA (XC2VP30).
Two Integrated PowerPC Processors.
Two memory blocks of 8Mx32 SDRAM memory each.
Virtex-II Pro FF1152 Development
Board
CoreConnect Architecture
Elements of the CoreConnect architecture:
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PLB (Processor Local Bus): high performance
synchronous bus designed for connection of
processors to high-performance peripherals devices.
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OPB (On-chip Peripheral Bus): general-purpose
synchronous bus designed for connection of onchip peripheral devices.
User Cores
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Objective: Add a User Core to an embedded
system, which implements a user-logic written in
vhdl.
The User core is to be attached to an embedded
processor bus, such as OPB or PLB.
There are several configurations that can be used
to connect user cores and user logic to an
embedded subsystem.
Connecting User Cores
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IPIF (IP Interface) – a portable, pre-designed bus
interface, that takes care of the bus interface signals,
bus protocol and other interface issues.
The IPIF presents an interface to the user logic called
the IP InterConnect (IPIC).
User logic is a logic that has been designed with an
IPIC interface to make use of the IPIF bus attachment
and other services.
User logic that is designed with an IPIC has the
advantage that it is portable and can be easily reused on
different processor buses by changing the IPIF to
which it is attached.
IPIF Scheme
User Core Reference Design
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simplifies the task of attaching the IPIF to user
logic.
The user core reference design is a VHDL file
that instantiates the IPIF and provides most of
the VHDL code required to create a user core.
The reference design provides a place to
instantiate the user logic, which can be VHDL
or a black box created from verilog, schematic,
etc.
User Core Reference Design Scheme
IPIF Example
Components - Hardware
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PPC 405
Plb2Opb Bridge
OPB
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PLB
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Uartlite : RS232
GPIO: LEDs
GPIO: Push Buttons
GPIO: DIPs
SDRAM (8M*32)
User Core
Bram
System DCM
System RESET
User Logic
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Receives 1 of 4 addresses
(“00”,”01”,”10”,”11”).
Each address correspond to a
LED.
The appropriate LED is
turned on/off according to
the LSB of the data.
The data returned is the data
received + const, when const
is determined by each
address.
(“00”: c=0,”01”: c=1,
“10”: c=2, “11”:c=3)
Bus2IP_Reset
Bus2IP_Clk
IP2Bus_
Data
Bus2IP_CS
User
Bus2IP_RdCE
Logic
Bus2IP_WrCE
Bus2IP_Addr
Bus2IP_Data
1 bit
4 bit
32 bit
LED
User Logic – VHDL (sample)
addr <= Bus2IP_Addr(28 to 29);
…
if Bus2IP_CS = '1' and Bus2IP_WrCE = '1‘ then
data <= Bus2IP_Data(24 to 31);
case addr is
when "00" => led0 <= Bus2IP_Data(31);
when "01" => led1 <= Bus2IP_Data(31);
when "10" => led2 <= Bus2IP_Data(31);
when "11" => led3 <= Bus2IP_Data(31);
when others => null;
end case;
end if;
….
Software – main
int main(){
Xuint32 Data=0, Res=0;
Xio_Address addr;
unsigned int usec_time=50000;
xil_print(“***MY OPB-PLB USER LOGIC***”);
check_sdram(); //calling check_sdram function
check_leds();
//calling check_leds function
addr=(Xio_Address)XPAR_PLB_USER_CORE_0_BASEADDR;
while(1){
Xio_Out32(addr, Data);
usleep(1);
Res=XIo_In32(addr);
xil_printf(“Res=%d\n\r”, Res);
usleep(usec_time);
}
}
Software – Memory Check
Function
void check_sdram(){
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temp=sdram_location;
// writing to all the memory addresses
for(loop_count=0;loop_count<mem_size;loop_count++){
*sdram_location = loop_count;
sdram_location++;
}
sdram_location=temp;
// reading from all the memory address and comparing to expacted
for(loop_count=0;loop_count<mem_size;loop_count++){
sdram_data_read = *sdram_location;
if(sdram_data_read!=loop_count) // failure – printing and exiting
else sdram_location++
}
xil_printf("SDRAM Test Passed\n\r");
}
Software – LEDs Check Function
void check_leds(){
…
XGpio_mSetDataDirection(XPAR_LEDS_4BIT_BASEADDR,
0x00);
for (count=0; count < 16; count++) {
XGpio_mSetDataReg(XPAR_LEDS_4BIT_BASEADDR,
~count);
usleep(100000);
xil_printf("Leds Count=%d\n\r",count);
}
xil_printf("LEDS Test Passed\n\r");
}
Output
Comments
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The VHDL code was tested using ModelSim.
Environment Testing – Using LEDs.
The Evaluation Board is new, therefore required
adjustments in the UCF file.
Other Debug tools, such as Chip-Scope, where
not used.
Other Examples
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Running Xilinx’s examples:
Basic Components (GPIO).
 Additional Memory.
 2 PowerPCs.
 IPIF example of LEDs Brightness.
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User Logic:
On OPB
 On PLB
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Goals – Second Part
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Implementing a signal processing
algorithm based on a FIR/IIR Filter with
Programmable coefficients.
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Simulating and checking the code of the
algorithm in hardware and software.
Running the algorithm on the board.
Project schedule
second semester
1st week:
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Defining the algorithm to be implemented.
2nd-3rd week:
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Design of the algorithm – block scheme.
4th week:
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Dividing the workload Software/Hardware and
Estimating the FPGA’s volume.
5th-6th week:
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Detailed design of each block from the scheme.
Project schedule
second semester
(cont)
7th-9th week:
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Hardware implementation
Software implementation.
10th-end:
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Simulation
Synthesis
Checking the algorithm using the evaluation board.
Thank You