Transcript No Slide Title

CPUs
Memory management
Caches
The Memory System
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Embedded systems and applications
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The memory system requirements: vary
considerably
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Simple blocks
Multiple types of memory
Caches
Write buffers
Virtual memory
Memory management units
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Memory management unit (MMU) translates addresses:
Protection checks
logical
address
CPU
memory
management
unit
physical
address
main
memory
Memory management tasks
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Allows programs to move in physical
memory during execution
Allows virtual memory:
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memory images kept in secondary storage;
images returned to main memory on demand
during execution
Page fault: request for location not resident
in memory
Address translation
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Requires some sort of register/table to allow
arbitrary mappings of logical to physical
addresses
Two basic schemes:
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segmented
paged
Segmentation and paging can be combined
(x86)
Segments and pages
page 1
page 2
segment 1
memory
segment 2
Segment address
translation
segment base address
logical address
+
segment lower bound
segment upper bound
range
check
physical address
range
error
Page address translation
page
offset
page i base
concatenate
page
offset
Page table organizations
page
descriptor
page descriptor
flat
tree
Caching address
translations
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Large translation tables require main
memory access
TLB: cache for address translation
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Typically small
ARM Memory Management
Unit
ARM Memory Management
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System control coprocessor(CP15)
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Registers
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Memory
Write Buffers
Caches
Up to 16 primary registers
Physical registers in CP15 more than 16
Register access instructions
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MCR (ARM to CP15)
MRC (CP15 to ARM)
Cached MMU memory
system
ARM Memory Management
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MMU can be enabled and disabled
Memory region types:
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section: 1 Mbytes block
large page: 64 Kbytes
small page: 4 Kbytes
tiny Page: 1 Kbytes
Two-level translation scheme (why?)
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First-level table
Second-level table
Page table size for 4KB pages : 220 X 4
bytes = 4 MB
ARM address translation
Translation table
base register
1st index 2nd index
offset
descriptor
1st level table
concatenate
descriptor
2nd level table
physical address
First-level descriptors
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AP: access permission
C,B: cachability and bufferability
Section descriptor and
translating section references
CP reg 2:
16 KB
boundary
Max: 16KB
4K Entries
1 MB block (section)
Coarse Page table
descriptor
4 K entries 256 entries
Max: 16KB
Max: 1KB
Fine page table descriptor
1 K entries
Max: 4 KB
Second-level descriptor
Translating large page
references
Access permissions
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System (S) and ROM (R) in CP15 register 1
TLB functions
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Invalidate instruction TLB
Invalidate instruction single entry
Invalidate entire data TLB
Invalidate data single entry
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TLB lockdown
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MPC 850 MMU
MPC850 MMU
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Does not support some PowerPC MMU
features
4-, 16-, 512- Kbyte, or 8-Mbyte pages
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Separate instruction and data MMUs
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1-KB subpages for 4-Kbyte pages
Can be disabled separately
Supports up to 16 virtual address spaces
Supports 16 access protection groups
MPC 850 MMU, cont’d
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Separate 8-entry, fully-associative data
translation lookaside buffer (DTLB) and
instruction TLB (ITLB)
High performance and low power
consumption
TLB locking, invalidation
Address Translation
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Translation disabled
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MSR[DR], MSR[IR]
Effective address = physical address
Translation enabled
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TLB
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SW handles the table lookup and TLB reload with
little HW assistance in the MPC 850
MMU supports a multiple virtual address space
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Address space ID (ASID)
Address Translation, cont’d
Not
implemented
in the DTLB
TLB operation
Current Address ID
Privilege level
8?
Translation Table (4 KB pages)
Translation Tables (1 KB pages)
Level-One descriptor
Level-Two Descriptor
4KB page
1KB protection
4KB page HW
assist
1KB subpage
Page Size
Programming Model
Programming Model (cont’d)
TLB operations
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tlbia: translation lookaside buffer invalidate
all
tlbie: translation lookaside buffer invalidate
entry
Locking TLB entries
Locking TLB Entries
IMMU control register
(MI_CTR bit 4)
DMMU control register
(MD_CTR bit 4)
DTLB reload