CS 2204

Digital Logic

and State Machine Design

Lab 8

As you wait for the lab to start : Is your laptop up-to-date ?

Experiment 5

Spring 2014

 Lab 8 Outline  Presentation   Analysis of the term project  Analysis of Block 1 16 ) of the term project (using

Term Project

pages 11 –   Analysis of Block 6 48 ) of the term project (using Implementing a machine player

Term Project

pages 38  A machine playing strategy Xilinx sequential circuit components  Individual work  Experiment 5  Develop the BCD up counter of the Information Gathering Subblock of Machine Player of the Ppm term project CS 2204 Spring 2014 Experiment 5 Lab 8 Page 2



Analysis of the Term Project



Polytechnic Playing Machine, Ppm

 The term project is human vs. machine 

The black-box view

From page 2 of the Term Project Handout

19 From the input devices 13

Ppm

To the output devices

Figure 1. The Ppm black box view.

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 3

LD0-LD2 on the FPGA board show the current state

Ppm Input/output relationship

Ppm operation diagram

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 4



The Ppm Digital System Partitioning

From page 9 of the Term Project Handout

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 5

 

Digital Systems



A digital system performs microoperations

 A digital system consists of digital circuits

A digital system consists of

 

A data unit



( datapath )

It performs microoperations

A control unit

 It controls the datapath CS 2204 Spring 2014 Experiment 5 Lab 8 Page 6



Digital Systems

 This first partitioning of a digital system is universal Other digital systems/ Input/Output devices Registers ALUs buses control signals status signals Data Unit (Datapath) Sequencer

Figure 7. A large scale view of a digital system.

   A microprocessor is a digital system An iPhone is a digital system A computer is a collection of digital systems Control Unit CS 2204 Spring 2014 Experiment 5 Lab 8 Page 7



Digital Systems



The Data Unit has registers , ALU s and buses to perform microoperations

   Registers keep (store) data (operands and results) Arithmetic Logic Units ( ALUs ) perform additions, subtractions, multiplications, ANDS, ORs, etc.

Buses interconnect registers and ALUs CS 2204 Spring 2014 Experiment 5 Lab 8 Page 8

 Digital Systems  The  Control Unit ( Sequencer ) The control unit determines the sequence on the current state and status signals  of microoperations based In each state , it enables happen in the data unit the microoperations of that state to based on the status signals  • Microoperations must start and end at the right time at the right time with correct inputs with correct outputs  We should not lose data and we should not use old data • Glitches , gate delays  must be accounted for When we design it, we account for every possible gate delay The control unit also determines which state is next : Next State CS 2204 Spring 2014 Experiment 5 Lab 8 Page 9



Digital Systems

 The   Control Unit ( Sequencer ) The Logic state register indicates the current state to generate the more irregular control signals than the Data Unit and the next state Status signals (From the Data Unit) Control signal and next state value generation circuits Current State State Register

Figure 8. A general view of the sequencer.

Control signals (To the Data Unit) Next State CS 2204 Spring 2014 Experiment 5 Lab 8 Page 10



Digital Systems

 The  Control Unit Hardwiring ( Sequencer ) design vs microprogramming Gate/FF networks = random logic = irregular Status signals Control signals Random Logic Memory bits generate control signals and NS Status signals Control signals Memory Look-up table Highly regular but slower Current State State Register Next State Current State State Register Next State

Not as regular as the datapath a. A general view of a hardwired sequencer.

b. A general view of a microprogrammed sequencer.

Figure 9. Digital system sequencers.

 Since our Ppm system is simple , we use hardwiring will concentrate on hardwiring from this point on and so we CS 2204 Spring 2014 Experiment 5 Lab 8 Page 11



Digital Systems

 The  Control Unit ( Sequencer ) design Hardwired Control Unit design  First partitioning on the Control Unit • Control Signal generation • Next State Generation Subblock Subblock Often a decoder used to generate the control and next state signals is Status signals (From the Data Unit) Control signal and next state value generation circuits Often a counter is used instead of a register since we frequently trace the states sequentially Current State State Register

Figure 8. A general view of the sequencer.

Control signals (To the Data Unit) Next State CS 2204 Spring 2014 Experiment 5 Lab 8 Page 12



Digital Systems

 The  Control Unit ( Sequencer ) design Hardwired Control Unit design  Often a counter + decoder combination is used in the sequencer If it is state 0 , S0 is 1 Next state Current state Status signals n Data Load clock n D0 S0 D1 S1 D3

.....

S2 (n-1) Control Signals & Next State Circuits Control signals Next State CS 2204 Spring 2014 Experiment 5 Lab 8 Page 13



The Ppm Control Unit



Block 1 , the Control Unit (the sequencer)

20 23

Block 1 

It controls



the Data Unit

It determines  the sequence of microoperations Which microoperation happens when CS 2204 Spring 2014 Experiment 5 Lab 8 Page 14

 

The Ppm Control Unit



Block 1 , the Control Unit (the sequencer)

The control unit microoperations   determines the sequence based on the status of signals Implemented by using the finite-state machine ( FSM ) technique Uses hardwiring • Gate and flip-flip networks generate control signals  Partitioned • • into Control Signal generation Next State Generation Subblock Subblock CS 2204 Spring 2014 Experiment 5 Lab 8 Page 15



The Ppm Control Unit

 Block 1 , the Control Unit (the sequencer) Gate and flip-flop networks generate control and next state signals Hardwired Control Unit

Control signals Control Signal Generation Subblock Next State Generation Subblock Counter Decoder combination to keep track of the current state

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 16



Digital Systems



How can we

design



a digital system ?

If the digital system is complex  It is the case with real • Write an HDL ► ► program VHDL Verilog program HDL program chips, such as microprocessors CS 2204 Spring 2014 Experiment 5 Lab 8 Page 17



Digital Systems



How can we design



a digital system ?

If the digital system is simple  It is the case with our term project • Use the finite state machine (

FSM

) technique • ► One obtains the operation diagram FSM state diagram with same then converts it to a number of states ► We Get draw a finite-state diagram a finite-state diagram directly from the operation diagram CS 2204 Spring 2014 Experiment 5 Lab 8 Page 18



Digital Systems

 How can we design  a digital system ?

If the digital system is simple  It is the case with our term project • Use the finite state machine (

FSM

) technique ► Obtain a high-level state diagram directly from the operation diagram  Use the Register-Transfer Level ( RTL ) notation ► ► ► Obtain the datapath from the high-level state diagram Obtain the low-level state diagram from the datapath and high-level state diagram Obtain the Control Unit Register ← Source Wire / bus = Source CS 2204 Spring 2014 Experiment 5 Lab 8 Page 19



Digital System Design Using FSM

 The  Data Unit ( Datapath ) The data unit control signals performs microoperations  based on the The data unit goes through states • The high-level state diagram ► ► indicates the microoperations Each state indicates the microoperations to perform in that clock period  The Data Unit generates status signals as it performs microoperations In each state , the control signals indicate which microoperations should happen  The low-level state diagram indicates which control signals should be active CS 2204 Spring 2014 Experiment 5 Lab 8 Page 20

 Digital System Design Using FSM  The  Control Unit ( Sequencer ) The control unit on the status determines the sequence signals  of microoperations based The control unit goes through states • • • Each state has a unique ► number to identify The state register value is the current state number In each data unit state , it enables the microoperations of that state to happen in the based on the status signals It generates the control signals and next state signals timely Status signals (From the Data Unit) Control signals (To the Data Unit) Control signal and next state value generation circuits Current State State Register

Figure 8. A general view of the sequencer.

Next State CS 2204 Spring 2014 Experiment 5 Lab 8 Page 21



Digital System Design Using

FSM



The



Control Unit ( Sequencer )

The sequencer  is treated as a state machine A low-level state diagram (with finite number of states ) shows which microoperation happens when in terms of control signals • Each state shows ► ► Which control signal is active Which state to go to next based on status signals Status signals (From the Data Unit) Control signal and next state value generation circuits Current State State Register Control signals (To the Data Unit) Next State

Figure 8. A general view of the sequencer.

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 22

 

Digital System Design Using FSM

1.

On paper 2.

3.

4.

5.

6.

Start with the relationship Convert the textual input/output relationship operation diagram Convert the operation diagram diagram

states

 From the high-level state diagram , obtain the datapath From the obtain the low-level state diagram Decide about how to ( sequencer )  black box A diagram with

finite

view and the textual input/output of the digital system with microoperations with the number of states high-level state diagram implement to an to a high-level state

same

number of and the datapath , the control unit Hardwiring • • or microprogramming Hardwiring is acceptable if it is It is the case with the Ppm not a complex digital system term project CS 2204 Spring 2014 Experiment 5 Lab 8 Page 23

  

Digital System Design Using FSM

On paper 7.

Implement the sequencer which is treated as a state machine   The number of states) shows which microoperation happens when • • Convert control signal and next state information of the low level state diagram • • low-level state diagram Each state shows ► ► Which Which control signal (a state diagram with is active state to go to next based on status signals Each state has a unique number to identify ► The state register value is the current state to sequencer hardware Place the counter ( state register ) + decoder hardwiring Obtain ► is used Expressions Obtain gate networks of the sequencer finite combination if  Start implementing the circuits on computer Start drawing the schematics by using the design on paper CS 2204 Spring 2014 Experiment 5 Lab 8 Page 24



Digital System Design Using FSM

K 1.

Start with the relationship black box view and the textual input/output of the digital system The black-box view

8

Clock Digital System OUT

3

Valid The Textual Input/Output Relationship • • Starting with the • • • Reset state Input 8 numbers on K in eight successive clock periods Determine sequence number of largest Output in 9 th valid the signal sequence number number of the largest number clock period and also a one clock period long Repeat these every 9 clock periods • Keep the output value at 0 until the next output value is calculated CS 2204 Spring 2014 Experiment 5 Lab 8 Page 25

 Clock Digital System Design Using FSM 1.

Start with the relationship black box view and the textual input/output of the digital system 9 clock period cycle Cp 1 Cp 2 Cp 3 Cp 4 Cp 5 Cp 6 Cp 7 Cp 8 Cp 9 Output Snum N0 Store it N1 N2 Compare Compare & store & store N3 Compare & store N4 Compare & store N5 Compare & store N6 Compare & store N7 Compare & store Output SNUM OUT Valid Output zero until the new result is obtained OUT CS 2204 Spring 2014 Experiment 5 Lab 8 Page 26

2.

Convert the textual input/output relationship to an operation diagram • • After Reset • Input 8 numbers on K • • Choose the Determine largest sequence number ( SNUM ) • of largest number Output SNUM in 9 th clock period and also a one clock period long valid signal Repeat every 9 clock periods • Keep the output value at 0 until the next output value is calculated

0

Store 1 st number & store SNUM as 0

1

If K > 1 st number then store K & update SNUM

2

If K > current largest then store K & update SNUM

3

If K > current largest then store K & update SNUM

4

If K > current largest then store K & update SNUM

5

If K > current largest then store K & update SNUM

6

If K > current largest then store K & update SNUM

7

If K > current largest then store K & update SNUM

8

Output SNUM and Valid CS 2204 Spring 2014 Experiment 5 Lab 8 Page 27

3.

Convert diagram with the states the operation diagram to a high-level state with microoperations same number of

0

A  K ; B  0

1

If K > A then A  K & B  1

2

If K > A then A  K & B  2

3

If K > A then A  K & B  3

4

If K > A then A  K & B  4

5

If K > A then A  K & B  5

6

If K > A then A  K & B  6

7

If K > A then A  K & B  7

8

OUT = B ; Valid = 1 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 28

3.

Convert diagram with the states the operation diagram to a high-level state with microoperations same number of Register

0

A  K ; B  0

1

If K > A then A  K & B  1

2

If K > A then A  K & B  2

3

If K > A then A  K & B  3

4

If K > A then A  K & B  4

5

If K > A then A  K & B  5

6

If K > A then A  K & B  6

7

If K > A then A  K & B  7 Wires

8

OUT = B ; Valid = 1 RTL notation CS 2204 Spring 2014 Experiment 5 Lab 8 Page 29

4.

Obtain the datapath from the high-level state diagram

0

A  K ; B  0

1

If K > A then A  K & B  1

2

If K > A then A  K & B  2

3

If K > A then A  K & B  3

4

If K > A then A  K & B  4

5

If K > A then A  K & B  5

6

If K > A then A  K & B  6

7

If K > A then A  K & B  7

8

OUT = B ; Valid = 1 Clock SNUM

3

Clock Store B 0

3 3 1 0

3-bit 2-to-1 MUX Sel K A

8

OUT

3

Store

8

Val

B

Compare

AGTB A

Gt Valid CS 2204 Spring 2014 Experiment 5 Lab 8 Page 30

4.

Obtain the datapath from the high-level state diagram Remember :  Registers need Store    MUXes need ALUs need Others may Select ALUcontrol signals signals signals need Enable signals  Special signals may be needed Clock K A

8

Store

8 3

Clock Snum Val signals signal SNUM Store B 0

3 3 1 0

3-bit 2-to-1 MUX Registers Sel OUT

3 B

Compare

AGTB A

Val Gt Valid CS 2204 Spring 2014 Experiment 5 Lab 8 Page 31

5.

Obtain the low-level state diagram from the high-level state diagram and the datapath

0

Store = 1 ; SNUM = 0 ; Sel = 0 SNUM

1

= 1 ; Sel = 0 If Gt == 1 then Store = 1

2

SNUM = 2 ; Sel = 0 ; If Gt == 1 then Store = 1

3

SNUM = 3 ; Sel = 0 ; If Gt == 1 then Store = 1 SNUM

4

= 4 ; Sel = 0 ; If Gt == 1 then Store = 1 SNUM

5

= 5 ; Sel = 0 ; If Gt == 1 then Store = 1 SNUM

6

= 6 ; Sel = 0 ; If Gt == 1 then Store = 1 SNUM

7

= 7 ; Sel = 0 ; If Gt == 1 then Store = 1

8

Val = 1 ; Sel = 1 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 32

6.

Decide about how to implement the control unit ( sequencer ) K

8

Clock Data Unit OUT

3

Gt Store Sel Val Valid 3 SNUM Clock Control Unit Six control signals One status signal We use hardwiring since it is a very simple digital system CS 2204 Spring 2014 Experiment 5 Lab 8 Page 33

7.

Convert control signal and next state information of the low-level state diagram to sequencer hardware How do we implement the round robin trace of the states ?

0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 We need a combination of ► 4-bit Up counter ► 3-to-8 Decoder To keep track of the current state CS 2204 Spring 2014 Experiment 5 Lab 8 Page 34

7.

Convert diagram  control signal and next state information of the low-level state to sequencer hardware Place the counter+decoder combination if hardwiring is used How do we implement the round robin trace of the states ?

0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 We need a combination of ► 4-bit Up counter ► 3-to-8 Decoder To keep track of the current state We have to load 0 after the count is 8 !

0 0 0 0 LD STC3 Clock D0 D1 D2 D3 Q0 STC0 A0 Q1 STC1 A1 Q2 STC2 A2 Q3 STC3 E D0 D1 D2 D3 D4 D5 D6 D7 S0 S1 S2 S3 S4 S5 S6 S7 S8 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 35

7.

Convert control signal and next state information of the low-level state diagram to sequencer hardware  Place the counter+decoder combination if hardwiring is used  Obtain Expressions Store is 1 when it is ► ► State 0 OR (state 1 OR state 2 OR state 1 OR state 3 OR state 4 OR state 5 OR state 6 OR state 7) AND Gt = 1 Store is 1 when it is ► ► State 0 OR ( NOT state 8) AND Gt = 1 Store = S0 + (S8 Gt ) CS 2204 Spring 2014 Experiment 5 Lab 8 Page 36

7.

Convert control signal and next state information of the low-level state diagram to sequencer hardware  Place the counter+decoder is used • Obtain combination if hardwiring Expressions • Obtain gate networks of the sequencer Store = S0 + S8 Gt Store S0 Control Unit Gt S8 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 37

7.

Convert control signal and next state information of the low-level state diagram to sequencer hardware  Place the counter+decoder combination if hardwiring is used  Obtain Expressions Sel is 1 when ► It is state 8 Sel = S8 Val is 1 when ► It is state 8 Val = S8 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 38

7.

Convert diagram  Place • control signal and next state information of the to sequencer hardware the counter+decoder combination if hardwiring Obtain • Expressions Obtain gate networks of the sequencer is used low-level state Sel = S8 Val = S8 Sel Val S8 S8 Control Unit CS 2204 Spring 2014 Experiment 5 Lab 8 Page 39

7.

Convert control signal and next state information of the low-level state diagram to sequencer hardware  Place the counter+decoder combination if hardwiring is used  Obtain Expressions SNUM = 0 when it is state 0 SNUM = 1 when it is state 1 SNUM = 2 when it is state 2 SNUM = 3 when it is state 2 SNUM = 4 when it is state 4 SNUM = 5 when it is state 5 SNUM = 6 when it is state 6 SNUM = 7 when it is state 7 SNUM2 SNUM1 = STC2 = STC1 SNUM0 = STC0 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 40

7.

Convert diagram  Place • control signal and next state information of the to sequencer hardware the counter+decoder combination if hardwiring Obtain • Expressions Obtain gate networks of the sequencer is used low-level state SNUM2 = STC2 SNUM1 = STC1 SNUM0 = STC0 SNUM2 SNUM1 SNUM0 STC2 STC1 STC0 Control Unit CS 2204 Spring 2014 Experiment 5 Lab 8 Page 41

7.

Convert control signal and next state information of the low-level state diagram to sequencer hardware

Control Unit

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 42

 Digital System Design Using FSM   Final digital system design on paper Start implementing the circuits on computer  Start drawing the schematics by using the design on paper Datapath Gt Control Unit CS 2204 Spring 2014 Experiment 5 Lab 8 Page 43



Machine Play Block, Block 6

 How  is it designed ?

Machine player gathers   information and then decides It must have • • It must have inputs to gather information The number of inputs depends on the strategy But, a few inputs are required for some strategies outputs to be able to play the game • • The number of outputs depends on the strategy But, a few outputs are required for any strategy

?

Block 6

?

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 44



Machine Play Block, Block 6

 How  is it designed ?

Machine player gathers    information and then decides It must have a subblock to gather information • Information gathering is a major operation It must have a subblock to decide how to play • Decision making is another major operation Any other subblock (major operation) ?

?

Block 6

?

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 45

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   Machine player stays at least gather information and decide one clock period in state 4 to It stays done   more than one clock period if gathering information is sequentially • Because the information needed is must be collected one by one not Collecting information in parallel requires The loop-back arrow in state 4 available all at once and so a lot of hardware !

indicates that more than once clock period is spent CS 2204 Spring 2014 Experiment 5 Lab 8 Page 46

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   Machine player stays at least gather information and decide one clock period in state 4 to It stays done   more than one clock period if gathering information is sequentially • It collects the information in a number of clock periods and then in one more clock period it plays The course web site machine player is like that It collects information for 9 th clock period !

8 clock periods and decides to play/skip in the CS 2204 Spring 2014 Experiment 5 Lab 8 Page 47

  Machine Play Block, Block 6  The machine player is active in state 4 to think and play/skip The course web site machine player collects information for clock periods and decides to play/skip in the 9 th clock period !

8 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 48

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   Machine player stays at least gather information and decide one clock period in state 4 to It stays done  more than one clock period if gathering information is sequentially • • We need a controlling major operation to determine the sequence of information gathering and then deciding !

A controller subblock is needed in addition to the information gathering and decision making blocks !

Since the machine player is a complex sequential circuit with a controller then Block 6 is a tiny digital system itself CS 2204 Spring 2014 Experiment 5 Lab 8 Page 49

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   Machine player stays at least gather information and decide one clock period in state 4 to A  controller subblock is needed in addition to the information gathering and decision making blocks !

Since the machine player is a complex sequential circuit with a controller then Block 6 is a tiny digital system itself Block 6 Information Gathering Sequencing Decision Making Data Unit Control Unit CS 2204 Spring 2014 Experiment 5 Lab 8 Page 50

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   It stays more than one clock period if gathering information is done sequentially The required inputs if it stays more than one clock period  Other inputs are needed to gather information

.

.

.

P2sturn

Block 6

Clearp2ffs P2clk

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 51

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   Machine player stays at least gather information and decide one clock period in state 4 to If the information needed is available machine player stays   one clock period all at once , then the in state 4 • It collects the information and decides to play/skip in period !

The loop-back arrow is Today’s machine player is a simple one and so takes period !

not needed then !

one clock only one clock CS 2204 Spring 2014 Experiment 5 Lab 8 Page 52

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   Machine player stays at least gather information and decide one clock period in state 4 to If the information needed is available machine player stays  one clock period all at once , then the in state 4 • • • • We do not need a controlling major operation to determine the sequence of information gathering and then deciding !

A controller block is not needed in addition to the information gathering and decision making blocks !

The machine player can be a information and decides how to play The machine player can have decide how to play combinational circuit that gathers in one clock period sequential in one clock period circuits to gather information and Because, the information needed to make a decision is available all at once CS 2204 Spring 2014 Experiment 5 Lab 8 Page 53

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   Machine player stays at least gather information and decide one clock period in state 4 to If the information needed is available machine player stays  one clock period all at once , then the in state 4 Since the machine player is a combinational circuit, there are only two subblocks in Block 6 Block 6 Information Gathering Decision Making CS 2204 Spring 2014 Experiment 5 Lab 8 Page 54

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   The machine player stays one clock period in state 4 There is  no required input if it stays one clock period But, other inputs are needed to gather information

.

.

.

.

Block 6 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 55

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   How can the machine player periods) ?

indicate how it plays after collecting information and deciding (taking one or more clock It needs to have   outputs to indicate its decision • • • If it decides to play the random digit Output lines to indicate which position : P2SEL An output line to indicate whether it is an addition or direct play : An output line to indicate that it is playing, not skipping : P2played • If it decides to skip An output line to indicate it is skipping : P2skip P2add CS 2204 Spring 2014 Experiment 5 Lab 8 Page 56

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   How can the machine player indicate how it plays after collecting information and deciding (taking one or more clock periods) ?

It needs to have  outputs to indicate its decision • The required outputs whether it stays one clock period or longer Other outputs may be needed for the strategy, but not recommended 4

P2SEL

Block 6

P2add P2played .

.

P2skip

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 57

  Machine Play Block, Block 6  The machine player is active in state 4 to think and play/skip It needs to have outputs to indicate its decision  The required outputs whether it stays one clock period or longer 4 P2SEL has a

1

corresponding to the position played when the machine player plays the random digit Block 6

.

.

P2SEL P2add P2played P2skip

P2add is

1

if the machine player adds the random digit to a display P2played is

1

if the machine player plays the random digit on a display P2skip is

1

if the machine player skips the plays CS 2204 Spring 2014 Experiment 5 Lab 8 Page 58

 Machine Play Block, Block 6  Let’s player design  a machine player slightly more complex than last week’s machine To design it we  We develop must have a playing strategy !

a machine player strategy then !

There is a zero display ?

A simple playing strategy !

N Y RD > 3 ?

Play on the (rightmost) zero position directly (Action 3) N Y Leftmost bit of a 4-bit random value is 1 ?

N Y Play randomly using a 4-bit random value as described below (Action 0) ?

Skip (Action 1)

Block 6

Play on the (rightmost) largest position with an addition (Action 2) ?

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 59

 Machine Play Block, Block 6  Let’s design a machine player slightly more complex than last week’s machine player  To design it we must have a playing strategy !

 Random Value Let’s analyze the strategy • • If there is a zero display, it plays on the zero If the random digit is greater than 3, it plays addition • • display position directly on the largest display position with an If the leftmost bit of a 4-bit random value is 1, it skips Otherwise, it plays on a position indicated by the middle two bits of the 4-bit random value and whether to do an addition is indicated by the rightmost bit of the 4-bit random value such that if it is 0, it plays directly , else with an addition RV3 RV2 RV1 RV0 1 : Skip 0 : Play 00 : Position 0 01 : Position 1 10 : Position 2 11 : Position 3 0 : Play directly 1 : Play by adding

?

?

Block 6 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 60

 Machine Play Block, Block 6  Let’s design a machine player slightly more complex than last week’s machine player  To design it we must have a playing strategy !

 Random Value How do we implement the random value ?

• We will use the technique used for generating random digits for the game • • We will use a high speed modulo-10 up counter that will continuously count such that we cannot predict its output !

The clock input will be the same as the clock input of the random digit generation counter (U119) in Block 4 : Rdclk RV3 RV2 RV1 RV0 1 : Skip 0 : Play 00 : Position 0 01 : Position 1 10 : Position 2 11 : Position 3 1 : Play directly 0 : Play by adding

?

?

Block 6 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 61

 Machine Play Block, Block 6  To design it we must have a playing strategy !

 We develop a machine player strategy then ! We need to collect the display values and random digit : DISP , RD We input 16 bits : DISP 15 – DISP0 We input 4 bits : RD3 – RD0 We input a Rdclk clock signal for the modulo-10 up counter :

?

Block 6

?

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 62

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   Machine player stays at least gather information and decide one clock period in state 4 to If the information needed is available machine player stays  one clock period The DISP and RD lines are available more than one clock period all at once in state 4 all at once , so no , then the need to have CS 2204 Spring 2014 Experiment 5 Lab 8 Page 63

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   The DISP information is available machine player stays one clock period all at once in state 4 , and so the We do  not need a controlling major operation to determine the sequence of information gathering and then deciding !

The machine player hass a sequential circuit but it gathers information and decides how to play in one clock period since the information collected ( DISP and RD ) is available all at once CS 2204 Spring 2014 Experiment 5 Lab 8 Page 64

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   The DISP information is available machine player stays one clock period all at once in state 4 , and so the Since the machine player there are only two takes only one clock period to play , subblocks in Block 6 Block 6 Information Gathering Decision Making CS 2204 Spring 2014 Experiment 5 Lab 8 Page 65

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   The machine player stays It needs 16 DISP lines , one clock period 4 RD lines and in state 4 Rdclk line to be input

DISP RD Rdclk

16 4 Block 6 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 66

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip   How can the machine player indicate collecting information and deciding ?

It needs to have  outputs • • • • The required outputs

P2SEL P2add P2played P2skip

to indicate its decision Block 6 how it plays after 4

P2SEL P2add P2played .

.

P2skip

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 67

  Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip  The black box view of the machine player 16

DISP RD

4 Block 6

Rdclk

4 We must also output 8 P2CODE lines to avoid unnecessary warnings

P2SEL P2add P2played P2skip

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 68

  Machine Play Block, Block 6  The design of the machine player that is completely combinational The partitioning of the machine player block Block 6 4

DISP Rdclk

16 Information Gathering Decision Making 8

P2SEL P2add P2played P2skip P2CODE

4

RD

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 69

  Machine Play Block, Block 6  The design of the machine player that is completely combinational The Information Gathering Subblock Already designed 2

DISP

16 M2

LRGDISPPOS Aposzero

M3 2

ZERODISP Rdclk

RV Circuit 4

RV

Information Gathering CS 2204 Spring 2014 Experiment 5 Lab 8 Page 70

  Machine Play Block, Block 6  The design of the machine player that is completely combinational The Information Gathering Subblock

DISP

16 2

DISP Rdclk

16 M2 M3 RV Circuit 2 4

LRGDISPPOS Aposzero ZERODISP RV

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 71

 

Machine Play Block,

Block 6



The design of the machine player that is completely combinational

 The Information Gathering Subblock • • • The RV circuit is a modulo-10 up counter circuit Xilinx has a modulo-10 up counter !

But, in order to gain insight into sequential circuit design, we will implement the modulo-10 up counter by using a Xilinx modulo-16 up counter We will convert a Xilinx modulo-16 up counter to a modulo-10 up counter by using class notes !

Rdclk

RV Circuit 4

RV

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 72

  Machine Play Block, Block 6  The design of the machine player that is completely combinational The Decision Making Subblock 2 4

LRGDISPPOS Aposzero ZERODISP RD

2 4 Decision Making 8

P2SEL P2add P2played P2skip P2CODE

4

RV

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 73

 

Machine Play Block, Block 6

 Generating P2skip output We skip if    There is no zero display The random digit < 4 AND AND The leftmost bit of RV is 1

LRGDISPPOS Aposzero ZERODISP RD RV

2 2 4 4 Decision Making 4 8

P2SEL P2add P2played P2skip P2CODE

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 74

  Machine Play Block, Block 6  Generating P2skip output We skip if    There is no zero display The random digit < 4 AND AND The leftmost bit of RV is 1 P2skip = Aposzero RD3 RD2 RV3 RV3 Aposzero RD3 RD2 Random Digit < 4 ?

RD3 RD2 RD1 RD0 0 0 x x Aposzero is 0 AND RD3 = 0 AND RD2 = 0 AND RV3 is 1 P2skip CS 2204 Spring 2014 Experiment 5 Lab 8 Page 75

  Machine Play Block, Block 6  Generating P2played output We play if we do  NOT skip • • • That is, we play if There is a zero display The random digit > 3 OR OR The leftmost bit of RV is 0 P2played = P2skip P2skip P2played CS 2204 Spring 2014 Experiment 5 Lab 8 Page 76

  Machine Play Block, Block 6  Generating P2add output It plays with an addition if  There is no zero display AND • • RD > 3 OR RV 3 is 0 AND RV0 is 1 Random Digit > 3 ?

RD3 RD2 RD1 RD0 x 1 x x 1 x x x P2add = Aposzero ((RD3 + RD2) + (RV3 RV0)) CS 2204 Spring 2014 Experiment 5 Lab 8 Page 77

  Machine Play Block, Block 6  Generating P2add output It plays with an addition if  There is no zero display AND • • RD > 3 OR RV 3 is 0 AND RV0 is 1 Random Value RV3 RV2 RV1 RV0 1 : Skip 0 : Play 00 : Position 0 01 : Position 1 10 : Position 2 11 : Position 3 0 : Play directly 1 : Play by adding Random Digit > 3 ?

RD3 RD2 RD1 RD0 x 1 x x 1 x x x CS 2204 Spring 2014 Experiment 5 Lab 8 Page 78

  Machine Play Block, Block 6  Generating P2add output It plays with an addition if  There is no zero display AND • • RD > 3 OR RV 3 is 0 AND RV0 is 1 RV0 RV3 Random Digit > 3 ?

RD3 RD2 RD1 RD0 x 1 x x 1 x x x P2add = Aposzero ((RD3 + RD2) + (RV3 RV0)) Aposzero RD3 RD2 P2add CS 2204 Spring 2014 Experiment 5 Lab 8 Page 79

  Machine Play Block, Block 6  Generating P2SEL outputs P2SEL outputs depend on zero displays, RD and RV  There are three choices for P2SEL lines   • • • • If there is a zero display , it plays on the rightmost zero display position If there is no zero display AND RD > 3 , it plays on the rightmost largest display position If there is no zero display AND RD < 4 AND position indicated by the middle two RV lines RV3 is 0 , it plays on the We need to select between these three choices We need to use a MUX In general, if there are Subblock must have a to select !

multiple (Action 0, Action 1, Action 2, etc.) then, the Decision Making MUX !

actions that play the random digit CS 2204 Spring 2014 Experiment 5 Lab 8 Page 80

  Machine Play Block, Block 6  Generating P2SEL outputs P2SEL outputs depend on if there is a zero display  There are three choices for P2SEL lines  • We need to use a MUX to select !

We need a 2-bit 4-to-1 MUX !

D1

ZERODISP1 ZERODISP0

D0

LRGDISPPOS1

C1 2-bit Y1 C0

LRGDISPPOS0

A1 4-to-1 Y0

RV2

MUX

RV1

A0

P2POSSEL1 P2POSSEL0 Select1 Select0

Sel1 Sel0 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 81

  Machine Play Block, Block 6  Generating P2SEL outputs We need a 2-bit 4-to-1 MUX !

 We need two select lines !

• How do we generate Select1 and Select0 lines ?

ZERODISP1 ZERODISP0

D1 D0

LRGDISPPOS1

C1 2-bit Y1 C0

LRGDISPPOS0

A1 4-to-1 Y0

RV2

MUX

RV1

A0

P2POSSEL1 P2POSSEL0 Select1 Select0

Sel1 Sel0 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 82

  Machine Play Block, Block 6  Generating P2SEL outputs We need a 2-bit 4-to-1 MUX !

 We need two select lines !

• How do we generate Select1 When Aposzero = 1 then it is Action 3 and Select0 outputs ?

Select1 = 1 AND Select0 = 1 Select1 Select0 11 10 01 00 : ZERODISP : LRGDISPPOS : Unused : RV When Aposzero = 0 AND RD > 3 then Action 2 Select1 = 1 When Aposzero = 0 AND RD < 4 AND RV3 = 0 then Action 0 AND Select0 = 0 Select1 = 0 AND Select0 = 0 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 83

  Machine Play Block, Block 6  Generating P2SEL outputs We need a 2-bit 4-to-1 MUX !

 We need two select lines !

• How do we generate Select1 and Generate Action lines first Select0 outputs ?

When Aposzero = 1 Action 3 Aposzero Action3 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 84

  Machine Play Block, Block 6  Generating P2SEL outputs We need a 2-bit 4-to-1 MUX !

 We need two select lines !

• How do we generate Select1 and Select0 outputs ?

When Aposzero = 0 AND RD > 3 Action 2 Aposzero RD3 RD2 Action2 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 85

  Machine Play Block, Block 6  Generating P2SEL outputs We need a 2-bit 4-to-1 MUX !

 We need two select lines !

• How do we generate Select1 and Select0 outputs ?

Select1 = 1 AND Select0 = 1 when Action3 = 1 Select1 = 1 AND Select0 = 0 when Action3 = 0 AND Action2 = 1 Select1 = 0 AND Select0 = 0 when Action3 = 0 AND Action2 = 0 Select1 Select0 11 10 01 00 : ZERODISP : LRGDISPPOS : Unused : RV CS 2204 Spring 2014 Experiment 5 Lab 8 Page 86

  Machine Play Block, Block 6  Generating P2SEL outputs We need a 2-bit 4-to-1 MUX !

 We need two select lines !

• How do we generate Select1 and Select0 outputs ?

Select1 = 1 AND Select0 = 1 when Action3 = 1 Select1 = 1 AND Select0 = 0 when Action3 = 0 AND Action2 = 1 Select1 = 0 AND Select0 = 0 when Action3 = 0 AND Action2 = 0 Select1 Select0 11 10 01 00 : ZERODISP : LRGDISPPOS : Unused : RV Select1 = Action3 + Action2 Select1 = 1 when Action3 = 1 OR Action2 = 1 Action3 Action2 Select1 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 87

  Machine Play Block, Block 6  Generating P2SEL outputs We need a 2-bit 4-to-1 MUX !

 We need two select lines !

• How do we generate Select1 and Select0 outputs ?

Select1 = 1 AND Select0 = 1 when Action3 = 1 Select1 = 1 AND Select0 = 0 when Action3 = 0 AND Action2 = 1 Select1 = 0 AND Select0 = 0 when Action3 = 0 AND Action2 = 0 Select0 = 1 when Action3 = 1 Select0= Action3 Action3 Select0 Select1 Select0 11 10 01 00 : ZERODISP : LRGDISPPOS : Unused : RV CS 2204 Spring 2014 Experiment 5 Lab 8 Page 88

  Machine Play Block, Block 6  Generating P2SEL outputs P2SEL outputs depend on if there is a zero display  There are three choices for P2SEL lines    • • • We need to We need to select between three choices We need to use a We need a 2-bit 4-to-1 MUX !

The MUX outputs convert MUX to select !

P2POSSEL the 2-bit We need a 2-to-4 decoder !

lines P2POSSEL lines to 4 P2SEL lines Y3

P2SEL3

I1

P2POSSEL1

Y2

P2SEL2 P2POSSEL0

I0 2-to-4 Decoder Y1

P2SEL1

Y0

P2SEL0

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 89

  Machine Play Block, Block 6  Generating P2CODE outputs P2CODE outputs are always zero

0 0 0 0 0 0 0 0

2

LRGDISPPOS Aposzero ZERODISP

2 Decision Making 4 8

P2CODE7 P2CODE6 P2CODE5 P2CODE4 P2CODE3 P2CODE2 P2CODE1 P2CODE0 P2SEL P2add P2played P2skip P2CODE

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 90

  Machine Play Block, Block 6  The design of the machine player that is completely The Decision Making Subblock combinational CS 2204 Spring 2014 Experiment 5 Lab 8 Page 91

  Machine Play Block, Block 6 The design of the machine player that is completely combinational Information Gathering Decision Making CS 2204 Spring 2014 Experiment 5 Lab 8 Page 92



Machine Playing Strategies

 Teams have to come up with a primary playing  strategy   before they can design their machine player A playing strategy is shown as a graph   Conditions • shown as ovals Game situations Actions • • shown as rectangles Playing the random digit on a display Skipping the plays and consists of The graph is NOT  with respect to time The graph is with respect to game situations !

Teams must also have to come up with a strategy positions secondary to resolve game situations where the primary playing strategy results in multiple playable CS 2204 Spring 2014 Experiment 5 Lab 8 Page 93



Playing Strategy of Player 1 of Ppmmvsm

 Its Implementation

Play on the (rightmost) largest regular reward position (directly if equal) (Action 0)

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 94



A Machine Player Strategy



Its Implementation

Largest regular reward = 0 ?

N y Play on the (rightmost) largest regular reward position (directly if equal) (Action 0) Skip

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 95



A Machine Player Strategy



Its Implementation

CS 2204 Spring 2014 N Largest regular reward = 0 ?

Y Player 2 does not have (64) 10 or more points & there is a position with a zero and RD is not zero N Y Play on the (rightmost) largest regular reward position (directly if equal) (Action 0) Play on the (rightmost) zero position (directly if equal) (Action 1) Skip Experiment 5 Lab 8 Page 96



A Machine Player Strategy

Player 1 does not have (64) 10 Largest regular reward = 0 ?

N Y or more points & there is a position with a zero and RD is not zero Skip N Y Player 1 does not have (64) 10 or more points & the largest regular reward is less than (64) 10 N Play on the (rightmost) largest regular reward position (directly if equal) (Action 0) Y Play on the (rightmost) largest position (directly if equal) (Action 1) Play on the (rightmost) zero position directly (if equal) (Action 2)

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 97



A Machine Player Strategy



Its Implementation

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 98

 Playing Strategy of Term Project  Its Implementation

Decision making Sequencing Information gathering

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 99



Xilinx FFs, Registers, Counters

 

Many do not have direct set inputs together

 To avoid cases where both

They have either and direct clear

are active   A direct set  Or input A direct clear input CS 2204 Spring 2014 Experiment 5 Lab 8 Page 100



Xilinx FFs, Registers, Counters

 Direct set and direct clear inputs  Asynchronous   As we studied in class • If the direct input is active, it affects the output immediately The name of the FF, register, counter has a • “ C ” near the end if it is the direct clear input • ► FDC : a D FF with an asynchronous direct clear input “ P ” near the end if it is the direct set (preset) input ► FDP : a D FF with an asynchronous direct set input CS 2204 Spring 2014 Experiment 5 Lab 8 Page 101



Xilinx FFs, Registers, Counters

 Direct set and direct clear inputs  Synchronous   If the direct input is active, it affects the output when there is the active clock edge The name of the FF, register, counter has an • “ R ” near the end if it is the direct clear input ► FDR : a D FF with a synchronous direct clear input • “ S ” near the end if it is the direct set input ► FDS : a D FF with a synchronous set input CS 2204 Spring 2014 Experiment 5 Lab 8 Page 102



Xilinx FFs, Registers, Counters



Some of them have an additional input

 Clock Enable ( CE )   The name of the FF, register, counter ends with an “ E ” It controls the clock input • If it is 1 , the clock input gets the clock signal ► It can be clocked (stored) • If it is 0 , the clock input gets 0   ► It cannot be clocked (cannot be stored)

The CE input is connected the Store signal of a register

FDCE : A D FF with an asynchronous direct clear input and a clock enable input CS 2204 Spring 2014 Experiment 5 Lab 8 Page 103



Xilinx FFs, Registers, Counters

 Clock Enable ( CE )  FDCE : A D FF with an asynchronous direct clear input and a clock enable input CLR 1 0 0 0 0 CE X 1 1 1 0 D X 0 1 X X C X 0 X Q 0 (Store 0) 0 (Store 0) 1 (Store 1) NS NS CS 2204 Spring 2014 Experiment 5 Lab 8 Page 104



Xilinx FFs, Registers, Counters

 Clock Enable ( CE )  The clock enable is often connected the “ Store ” signal CE is equivalent to

a Storey0 Clock Reset y0 Storey0 Clock a D C y0 Q CLR Reset

This way of “ gating the clock ” is not recommended CS 2204 Spring 2014 Experiment 5 Lab 8 Page 105



Assignment by next lab

     Make sure that you have completed Experiment 1 , Experiment 2 , Experiment 3 and Experiment 4 The last day to submit Experiment 4 as a team is March 28, 2014 The last day to submit Experiment 5 as a team is April 4, 2014 It will be graded and returned by the following lab Develop the playing strategy of your machine player that will be designed starting next lab Submit your Experiment 4 during a lab session !

Not during Open Lab Hours !

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 106

Make sure Make sure you have the LABS account and see the S drive you have installed WebPACK 12.4 on your laptop Make sure you create a CS2204 folder on both Read slides at the end to learn about the software, Project Manager, Schematic design and other related topics Do not leave the lab before your partners finish ► Help your partners

QUESTIONS ?

Continue reading the Term Project handout

Digital Logic

and

State Machine Design

Think the machine player about strategy CS 2204 Spring 2014 Experiment 5 Lab 8 Page 107



Today’s Individual Xilinx Work



We will continue to study project



(analyze) the term

We will use our knowledge of sequential circuits to develop a machine player with two conditions and three actions  

Help our partners complete today’s project We will continue reading the Term Project handout

 Also read slides at the end to learn about the software, Project Manager, Schematic design and other related topics CS 2204 Spring 2014 Experiment 5 Lab 8 Page 108

 1.

Today’s Individual Xilinx Lab Work

Open

a)

the

ppm

project in the Open the Project Manager and then open the Ppm project in the exp4 exp4 folder folder

b) c)

Look at the six Ppm schematics

Enter the team information to the schematics if it has not been entered  Save the schematic if the team information is entered CS 2204 Spring 2014 Experiment 5 Lab 8 Page 109

 1.

Today’s Individual Xilinx Lab Work Open d) the ppm project in the exp4 folder Make sure Experiment 1, Experiment 2, Experiment 3 and Experiment 4 are completed  That is you have the following in Schematic 3 and a circuit in Schematic 6 on the next slide : Experiment 1 And the next slide Experiment 2 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 110

 1.

Today’s Individual Xilinx Lab Work Open d) the ppm project in the exp4 folder Make sure Experiment 1, Experiment 2, Experiment 3 and Experiment 4 are completed  That is you have the following on Schematic 6 and a circuit on Schematic 3o n the previous slide : Experiments 3 and 4 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 111

 1.

Today’s Individual Xilinx Lab Work  Make sure Experiment 1, Experiment 2, Experiment 3 and Experiment 4 are completed That is on the screen you have the following : Experiments 3 and 4 Experiment 1 Experiment 2 Make sure your circuits in blocks 3 and 6 follow the Term Project Check List handout CS 2204 Spring 2014 Experiment 5 Lab 8 Page 112

 1.

Today’s Individual Xilinx Lab Work Open d) the ppm project in the exp4 folder  Make sure Experiment 1, Experiment 2, Experiment 3 and Experiment 4 are completed If they are not • • • • Lab 4 Lab 5 Lab 6 complete finish the designs by studying presentation for Experiment 1 presentation for Experiment 2 presentation for Experiment 3 Lab 7 presentation for Experiment 4 Make sure your circuits in blocks 3 and 6 follow the Term Project Check List handout • So that eventually Block 3 and Block 6 look like as follows : Experiment 1 Experiment 2 Experiments 3 and 4 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 113

 2.

Today’s Individual Xilinx Lab Work

Submit the Experiment 4 project after deciding  Decide  whose project on the team will be submitted Block 3 and Block 6 must look like as follows : Make sure your circuits in blocks 3 and 6 follow the Term Project Check List handout Experiment 1 Experiment 2 Experiments 3 and 4 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 114

 2.

Today’s Individual Xilinx Lab Work Submit the Experiment 4 project after deciding whose project is the best to submit  Fill out a

Term Project Check List

handout before signaling to the TA  Block 3 and Block 6 must look like as follows : Make sure your circuits in blocks 3 and 6 follow the Term Project Check List handout Experiment 1 Experiment 2 Experiments 3 and 4 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 115

 3.

Today’s Individual Xilinx Lab Work

By using Microsoft and Xilinx ISE create

exp5

from 4.

5.

6.

  Remember that we must create a new project from an earlier one by using Microsoft and Xilinx ISE We will experiment with the Ppm schematics

Open the Ppm Look at the six project in exp5



Ppm schematics If it has not been entered, place your team info on the schematics

Save the schematic if you enter the team information CS 2204 Spring 2014 Experiment 5 Lab 8 Page 116

 7.

Today’s Individual Xilinx Lab Work

Switch to schematic 4

8.

9.

Zoom into the upper right area, containing the Random Digit Generation Subsubblock

 

There is a Xilinx

macro

(a Xilinx Design Block,

XDB

) with label U119

A BCD   Up Counter, CD4CE , in the subsubblock It counts up 0 to 9, inclusive • Its clock is always enabled (CE = 1) • Its direct clear input is always inactive (CLR = 0) It implements the BCD Up counter similar to the modulo-12 counter implemented in class • We used a generic counter in class See Block 4 on next three slides CS 2204 Spring 2014 Experiment 5 Lab 8 Page 117

 

Today’s Individual Xilinx Lab Work

Ppm Block 4 Xilinx BCD Up Counter CS 2204 Spring 2014 Experiment 5 Lab 8 Page 118

 

Today’s Individual Xilinx Lab Work

Ppm Block 4 Xilinx BCD Up Counter Xilinx Grd by the 4-bit registers which are stored (Get Random 3 random digits when Digit) is raised to 1 control unit when BTN1 or BTN2 is pressed CS 2204 Spring 2014 Experiment 5 Lab 8 Page 119



Today’s Individual Xilinx Lab Work



Ppm Block 4

Random Digit Counter outputs : RDC The Random Digit Clock at 192 Hz : Rdclk Xilinx BCD Up Counter CS 2204 Spring 2014 Experiment 5 Lab 8 Page 120



Today’s Individual Xilinx Lab Work

10.

Analyze the BCD up counter to determine how it is used  Why is it used ?

   In order to generate BCD random digits to play on the displays • These digits should not be predictable • • They should give the impression that they are random Generating a truly random digit is hard and out of our scope We then generate BCD pseudo-random • digits If a number of conditions are satisfied it gives the impression that the digits are random  We will refer to it as random digit even though it is pseudo-random The BCD up counter runs at a high speed and its output is stored as a random digit when BTN1 or BTN2 is pressed • The counter output stored is hard to predict by humans • If the human player presses BTN1 and BTN2 in irregular time intervals, the digits stored seem random !

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 121



Today’s Individual Xilinx Lab Work

10.

Analyze the BCD up counter to determine how it is used

 See the correspondence between this circuit and your class notes     The Xilinx counter is an Up have the U/D input counter and so does Its internal design is for BCD external gate is needed counting and so no not Do a Hierarchy Push Xilinx See the and see how it is implemented by internal circuit on next slide CS 2204 Spring 2014 Experiment 5 Lab 8 Page 122

 Today’s Individual Xilinx Lab Work 10.

Analyze the BCD up counter to determine how it is used  See the correspondence between this circuit and your class notes No T FFs !

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 123



Today’s Individual Xilinx Lab Work

10.

Analyze the BCD up counter to determine how it is   used Close the schematic of the internal circuit of the Xilinx BCD up counter It counts up at the rate of Rdclk  (Random digit clock) Rdclk    is generated in the Timing Subblock of schematic 2 Rdclk Rdclk Q1 is derived from a is derived from 32-bit frequency divider Q1 which is one of the outputs of a 16-bit Xilinx binary counter , CB16CE, U67 , that is one of the two counters of the 32-bit frequency divider has the frequency of 192 Hz in Block 2  ► The counter counts at a high rate The BCD counter output is stored on a register ( U120 ) when a random digit is needed !

• It is highly improbable that we can guess what its output will be when we store it CS 2204 Spring 2014 Experiment 5 Lab 8 Page 124



Today’s Individual Xilinx Lab Work

10.

Analyze the BCD up counter to determine how it is used  It counts up at the rate of Rdclk  (Random digit clock) Only three outputs of the counter, RDC1 , RDC2 stored on a Xilinx 4-bit register, FD4CE, U120  and RDC3 are The counter value is stored on the register as the random digit when Grd (Get random digit) is 1     The rightmost output of the counter, RDC0 , is not register !

stored on the If this output is connected to the register, the random digit is always odd (1, 3, 5, 7 and 9) It is a problem of the Xilinx software and so to get around it the register is connected Q7 from U67 in schematic 2 Outputs RDC1 and RDC3 are also used by the Code Digit generation circuit, M1 , in Block 4 to generate code digits CS 2204 Spring 2014 Experiment 5 Lab 8 Page 125



Today’s Individual Xilinx Lab Work

10.

Analyze the BCD up counter to determine how it is used    It counts up at the rate of Rdclk (Random digit clock) Search   for the inputs and outputs of the counter Confirm that component U67 in Block 2 generates the clock signal Q1 which is renamed as Rdclk by using a buffer Confirm that component U120 in Block 4 uses outputs RDC3 , RDC2 and RDC1  Confirm RDC1 also that component M1 in Block 4 uses outputs RDC3 To search for a wire click on Edit -> Find… or press Ctrl+F the wire with a name  Select the Nets mode   Select With Name Enter Rdclk and then press Enter and to find  The software will automatically switch to schematic 2 wires with this name and show the wires in yellow that has the CS 2204 Spring 2014 Experiment 5 Lab 8 Page 126



Today’s Individual Xilinx Lab Work

11.

Perform functional simulations on the Xilinx BCD counter  You will confirm the input/output relationship of the counter  • • Select the wires as follows RDCLK RDC line as the input as the four output lines CS 2204 Spring 2014 Experiment 5 Lab 8 Page 127



Today’s Individual Xilinx Lab Work

11.

Perform functional simulations on the Xilinx BCD counter   You will confirm the input/output relationship of the counter  RDCLK line as the input  RDC as the four output lines Start functional simulations  Click on Restart on the upper tool bar so that the starting time is 0 seconds  Change the observation duration time to 150ns during the simulations CS 2204 Spring 2014 Experiment 5 Lab 8 Page 128

 Today’s Individual Xilinx Lab Work 11.

 Perform functional simulations on the Xilinx BCD counter In order to simulate the counter, a clock signal must be input to the counter.

 Follow the steps to generate a clock signal as an input • Right click on the Rdclk and select Force Clock… CS 2204 Spring 2014 Experiment 5 Lab 8 Page 129



Today’s Individual Xilinx Lab Work

11.

Perform functional simulations on the Xilinx BCD  counter In order to simulate the counter, a clock signal must be input to the counter.

 Follow the steps to generate a clock signal as an input • • • The Define Clock window will pop up to be entered values Enter the following values in the window ► Leading Edge Value is 1 ► ► Trailing Edge Value is 0 Period is 10ns After you enter the values the Define Clock window will look like the one on the next slide CS 2204 Spring 2014 Experiment 5 Lab 8 Page 130

 Today’s Individual Xilinx Lab Work 11.

 Perform functional simulations on the Xilinx BCD counter In order to simulate the counter, a clock signal must be input to the counter.

 Follow the steps to generate a clock signal as an input CS 2204 Spring 2014 Experiment 5 Lab 8 Page 131

 Today’s Individual Xilinx Lab Work 11.

 Perform functional simulations on the Xilinx BCD counter In order to simulate the counter, a clock signal must be input to the counter.

 Follow the steps to generate a clock signal as an input 1 means the first edge of the simulation is a positive edge 0 means the second edge of the simulation is a negative edge Duty cycle is 50% means period is 1 and 50% 50% of the clock of the clock period is 0 The clock period duration is 10ns Therefore, the clock frequency is 100 MHz CS 2204 Spring 2014 Experiment 5 Lab 8 Page 132



Today’s Individual Xilinx Lab Work

11.

Perform functional simulations on the Xilinx BCD  counter In order to simulate the counter, a clock signal must be input to the counter.

 Follow the steps to generate a clock signal as an input : • Click OK to close the Define Clock window CS 2204 Spring 2014 Experiment 5 Lab 8 Page 133



Today’s Individual Xilinx Lab Work

11.

Perform functional simulations on the Xilinx BCD counter

 Click on the icon to do a simulation for 150ns  The simulator starts with the initial value of 0 • See the next slide that shows the simulation for 15 clock periods CS 2204 Spring 2014 Experiment 5 Lab 8 Page 134

 

Today’s Individual Xilinx Lab Work

The simulation window for the Xilinx BCD Counter 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 The first edge is a positive edge CS 2204 Spring 2014 Experiment 5 Lab 8 Page 135

 Today’s Individual Xilinx Lab Work 11.

 Perform functional simulations on the Xilinx BCD counter Click on the icon to continue the simulation for 150ns more  The simulation below shows the values for 30 clock periods CS 2204 Spring 2014 Experiment 5 Lab 8 Page 136

 Today’s Individual Xilinx Lab Work 12.

Draw the gate network of the BCD Up Counter by using your     class notes in schematic 6 You will implement the few  First draw the complete schematic on a your gates as possible You will need to design a circuit to generate the load signal counter to count up to 9, not to 15 class notes Compare your schematic with your partners’ and make sure the schematic is computer correct RV outputs by using a Xilinx counter and as sheet of paper by using before you start the design on your for the up Draw the schematic on your computer based on your design on the sheet  You will use the

Add Symbol

button on the leftmost side (or Ctrl+M )    to get the component list You will use the

Add Wire

button on the leftmost side (or To rotate components right press

ctrl-r

Ctrl+W ) to Note, wires  cannot be rotated But, by pulling from one end of a wire, it can be rotated !

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 137

 Today’s Individual Xilinx Lab Work 12.

    Draw the gate network of the BCD Up Counter by using your class notes in schematic 6  Move up and create space Do not left You can move the M2 and M3 circuits developed last two weeks to Draw Draw M2 and M3 circuits closer to each other to create more space change the Decision Making Subblock circuit from last week a divider line to separate the RV circuitry from M2 and M3 circuits a longer divider vertical line to separate the Information Gathering Subblock from the Decision Making Subblock Implement BCD Up counter in this area Make sure your circuits in Block 6 follow the Term Project Check List handout CS 2204 Spring 2014 Experiment 5 Lab 8 Page 138



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  Counter by You will use a Xilinx 4-bit modulo-16 counter called CB4CLE  It is a Loadable counter with asynchronous Clear , Synchronous Load and Clock Enable • • • Here is the meaning of the characters in its name     C B4 : It is a counter : 4-bitBinary counter, i.e. a divide-by-16 or modulo-16 counter C L : Asynchronous clear : Loadable synchronously  E : Clock Enable Its clock is positive -edge triggered See the next slide for a larger view CS 2204 Spring 2014 Experiment 5 Lab 8 Page 139



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  A Xilinx 4-bit modulo-16 counter Counter by CS 2204 Spring 2014 Experiment 5 Lab 8 Page 140



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up Counter by using your class notes schematic 6 in

 You will use a Xilinx 4-bit modulo-16 counter called CB4CLE  Observe • the internal structure of the Xilinx CB4CLE Do a Hierarchy Push ► It has 4 loadable T and see how it is implemented FFs !

► See internal implementation of Xilinx slide CB4CLE on the next CS 2204 Spring 2014 Experiment 5 Lab 8 Page 141

 Today’s Individual Xilinx Lab Work  Observe the internal structure of the Xilinx CB4CLE Xilinx T FFs FTCLEX CS 2204 Spring 2014 Experiment 5 Lab 8 Page 142



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  Counter by You will use a Xilinx 4-bit modulo-16 counter called CB4CLE  Observe the internal structure of the Xilinx FTCLEX • • Do a ► Hierarchy Push and see how it is implemented It is a Xilinx specific Toggle / Loadable Synchronous Load and Clock Enable FF with asynchronous Clear , ► It has 6  T inputs and only one output !

(Toggle) as the regular Toggle input      D L (Data) to load data (Load) to indicate when to load CE C (Clock Enable) (Clock) which is positive -edge triggered CLR (Clear) to asynchronously clear the FF See the next slide for a larger view CS 2204 Spring 2014 Experiment 5 Lab 8 Page 143



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  A Xilinx FTCLEX FF Counter by CS 2204 Spring 2014 Experiment 5 Lab 8 Page 144



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  Counter by In order to count Up and load, it has a T FF that is called FTCLEX  Observe the internal structure of the Xilinx FTCLEX FF • Do a Hierarchy Push ► ► and see how it is implemented It does not have a T FF !

See internal implementation of the Xilinx FTCLEX FF on the next slide CS 2204 Spring 2014 Experiment 5 Lab 8 Page 145



Today’s Individual Xilinx Lab Work

 Xilinx FTCLEX FF is not implemented as a T FF Xilinx MUX Xilinx D FF CS 2204 Spring 2014 Experiment 5 Lab 8 Page 146



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  Counter by How can we design a modulo-10 up counter by using a Xilinx CB4CLE counter ?  Let’s start with the simplest inputs to work on • • • The counter will count all the time and so its Clock Enable ( CE ) input is always enabled by connecting it to 1 permanently The counter will never be cleared and so its Clear ( CLR ) input will be disabled by connecting it to 0 permanently The counter uses Rdclk and so its Clock ( C ) input will be connected to Rdclk CS 2204 Spring 2014 Experiment 5 Lab 8 Page 147



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  Counter by How can we design a modulo-10 up counter by using a Xilinx CB4CLE counter ?  The Load circuitry will detect ( 9 ) on the four outputs and generate a 1 output since the CB4CLE has an active-high Load input  You will use an AND binary ( 1001 ) • gate to detect number 9 in Unsigned In class, number 12 in Unsigned Binary ( 1100 ) is detected • • • The detection circuit requires that two counter outputs be inverted In order to avoid using inverters, the AND4B2 which internally inverts two of the inputs gate is used Label the output of this AND gate Loadrvc , meaning “Load RV Counter ” CS 2204 Spring 2014 Experiment 5 Lab 8 Page 148



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up Counter by using your class notes in schematic 6  How can we design a modulo-10 up counter by using a Xilinx CB4CLE counter ?   When the counter is loaded, the value to load is ( 0000 ) • In class, we loaded ( 0001 ) to the counter All D inputs are permanently connected to 0  The outputs are labeled as RV3 , RV2 , RV1 and RV0 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 149



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  Counter by How can we design a modulo-10 up counter by using a Xilinx CB4CLE counter ?  First draw the complete schematic on a using your class notes and sheet of paper Xilinx component figures by  Compare your schematic with your partners and make sure the schematic is correct before you start the design on your computer CS 2204 Spring 2014 Experiment 5 Lab 8 Page 150



Today’s Individual Xilinx Lab Work

12.

Draw the gate network of the BCD Up using your class notes in schematic 6  Counter by How can we design a modulo-10 up counter by using a Xilinx CB4CLE  counter ? First draw the complete schematic on a using your class notes sheet of paper by   Then, draw the schematic based on your design on the sheet  You will use the

Add Symbol

button on the leftmost side • • • (or Ctrl+M ) to get the component list You will use the

Add Wire

button on the leftmost side (or Ctrl+W ) to draw wires To rotate components right press

ctrl-r

Note, wires cannot  be rotated But, by pulling from one end of a wire, it can be rotated !

Label the wires (inputs and outputs) based on your analysis in part (9) CS 2204 Spring 2014 Experiment 5 Lab 8 Page 151

 Today’s Individual Xilinx Lab Work 12.

Draw the gate network of the BCD Up Counter by using your class notes in schematic 6  Label • • • • • • the components We have to have a consistent way of labeling components We have to label the components in one subblock and then label the components in another subblock, sweeping the subblocks from left to right and top to bottom Therefore, we need to label the Information Gathering Subblock components and then label the components in the Decision Making Subblock Relabel U307 the 2-bit 4-to-1 MUX as U306 , 2-to-4 decoder as and the inverter as U308 in the Decision Making Subblock Label U304 the components of BCD Up counter starting at The last label of BCD Up counter implementation will be U305 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 152

 Today’s Individual Xilinx Lab Work 12.

Draw the gate network of the BCD Up Counter by using your class notes in schematic 6    Label the components   • At this point where the Decision Making Subblock is the same as the Experiment 4 circuit, component labels in Block 6 are from U289 through U308 Determine that there is no component labeled above the last component count of Experiment 5 How can I search for a component in the schematics ?

• To search for components click on Edit -> Find… or press Ctrl+F • • • to find the component with a label Select the Instance mode Select With Name Enter a label number and then press Enter Save the schematic See modified Block 6 on the next slide CS 2204 Spring 2014 Experiment 5 Lab 8 Page 153

 Today’s Individual Xilinx Lab Work 12.

Draw the gate network of the BCD Up Counter by using your class notes in schematic 6 Modulo-10 Up counter implemented

The Decision Making Subblock is the same as Experiment 4 for the time being !

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 154



Today’s Individual Xilinx Lab Work

13.

Do a schematic check on the new design

 

The schematic check is to see if there are simple errors to catch on all schematics

Select

Tools



Check Schematic

 • The Console panel will indicate that there are no errors but three warnings See the next slide CS 2204 Spring 2014 Experiment 5 Lab 8 Page 155

 Today’s Individual Xilinx Lab Work 13.

Do a schematic check on the new design  The schematic check is to see if there are simple errors to catch on  all schematics Read the bottom portion of the Console panel for warnings and correct • There are five warnings !

   The five warnings are OK since we do not need these outputs We will ignore these unneeded output warnings and decide there is nothing to correct Next Slide explains why we ignore them CS 2204 Spring 2014 Experiment 5 Lab 8 Page 156

 13.

Today’s Individual Xilinx Lab Work

  Do a schematic check on the new design  The schematic check is to see if there are simple errors to catch on all schematics You might wonder how the project works if wires are not connected to • The Xilinx software integrates all the schematics during its • implementation wires are placed, the software connects not Schematic checks do not  That is why perform after catch all the errors the Schematic checks we have to    Functional simulations Xilinx IMPLEMENTATIONs Timing simulations CS 2204 Spring 2014 Experiment 5 Lab 8 Page 157



Today’s Individual Xilinx Lab Work

14.

Perform functional simulations on this BCD Up counter in schematic 6 to verify that it is working  Note that to do functional simulations, you must perform a synthesis You will see that there are ReRun warnings There will be 60 130 warnings, many of them new due to copying this project from exp4 the synthesis so that you eliminate most of the new warnings after the second synthesis CS 2204 Spring 2014 Experiment 5 Lab 8 Page 158



Today’s Individual Xilinx Lab Work

14.

Perform functional simulations on this BCD Up counter in schematic 6 to verify that it is working  You will confirm the input/output relationship of the counter  • • • Select the wires as follows RDCLK line as the input LOADRVC as the output line RV as the four output lines CS 2204 Spring 2014 Experiment 5 Lab 8 Page 159



Today’s Individual Xilinx Lab Work

14.

Perform functional simulations is working on this BCD Up counter in schematic 6 to verify that it

   See part (11) about supplying the periodic clock signal Note that to catch possible mistakes we have to observe the Loadrvc line and verify that it is 1 when the counter reaches 9 each time Click on the icon to do a simulation for 150ns  The simulator starts with the initial value of 0 • See the next slide that shows the simulation for 15 clock periods CS 2204 Spring 2014 Experiment 5 Lab 8 Page 160

 

Today’s Individual Xilinx Lab Work

The simulation window for the Xilinx BCD Counter Loadrvc is 1 when the count is 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 The first edge is a positive edge CS 2204 Spring 2014 Experiment 5 Lab 8 Page 161

 Today’s Individual Xilinx Lab Work 14.

Perform functional simulations on this BCD Up counter in schematic 6 to verify that it is working  Click on the icon to continue the simulation for 150ns more  The simulation below shows the values for 30 clock periods Loadrvc is 1 when the count is 9 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 162



Today’s Individual Xilinx Lab Work

14.

Perform functional simulations is working on this BCD Up counter in schematic 6 to verify that it

  If you catch errors correct them on schematic 6 Before completing this step, make sure the circuit in schematic 6 is

beautified

and the schematic is saved again CS 2204 Spring 2014 Experiment 5 Lab 8 Page 163



Today’s Individual Xilinx Lab Work

15.

Modify the Decision Making Subblock strategy as explained on to complete the implementation of the new machine playing slides 59 to 92  Modify the Decision Making Subblock schematic     • • Draw the new schematic by following slides 69 to 92 Appropriately label the components such that the highest components label is U315 Note that there are two buffers used but their labeling is different Beautify your circuits Save See the schematic modified Block 6 on the next slide CS 2204 Spring 2014 Experiment 5 Lab 8 Page 164

 15.

Today’s Individual Xilinx Lab Work Modify the Decision Making Subblock slides 59 to 92 to complete the implementation of the new machine playing strategy as explained on CS 2204 Spring 2014 Experiment 5 Lab 8 Page 165



Today’s Individual Xilinx Lab Work

16.

Do a schematic check on the new design    There will be 0 errors and 5 warnings The 5 warnings are the same as in step 13 above Since all these five warnings are acceptable there is nothing to correct CS 2204 Spring 2014 Experiment 5 Lab 8 Page 166



Today’s Individual Xilinx Lab Work

17.

Perform functional simulations on the new design to verify that it is working

   In order to do logic simulations, perform a synthesis The number of synthesis warnings is 58 Perform logic simulations to observe that the machine player follows the playing strategy CS 2204 Spring 2014 Experiment 5 Lab 8 Page 167



Today’s Individual Xilinx Lab Work

18.

Perform a Xilinx IMPLEMENTATION • • • • Xilinx IMPLEMENTATION is changed is required after a schematic When we indicate IMPLEMENTATION we mean Synthesis , Implement Design and Generate Programming File steps we see on the Project Navigator window Since we changed schematic 6 we have to do a Xilinx IMPLEMENTATION Xilinx IMPLEMENTATIONS are needed for three reasons    Catching more errors not discovered via schematic checks and functional simulations as the software analyzes the schematics Catching even more errors by doing timing simulations possible after the Xilinx IMPLEMENTATION Creating a new bit file CS 2204 Spring 2014 Experiment 5 Lab 8 Page 168



Today’s Individual Xilinx Lab Work

18.

Perform a Xilinx IMPLEMENTATION • • Xilinx IMPLEMENTATION maps FPGA resources (CLBs and wires)  the schematics to the If the mapping is complete then there are

no

errors but there can be warnings • Mapping allows real components to be considered, hence timing simulations • • Xilinx IMPLEMENTATION  consists of 3 major steps Synthesis to translate the schematic to a netlist file after converting the schematic to a VHDL file Implement Design which consists of • Translate , Map , Place & Route Generate Programming File to generate the bit file CS 2204 Spring 2014 Experiment 5 Lab 8 Page 169

 Today’s Individual Xilinx Lab Work 18.

Perform a Xilinx IMPLEMENTATION      Click on Design Summary (out of date) to be able to see the number of errors and warnings Right click on Generate Programming File and select Rerun All • We will do the Synthesis, Implement Design and Generate Programming File steps altogether Even though we already did the synthesis, we will do it again to get practice on this as we will do it many times Wait until the IMPLEMENTATION completes • If it does  not complete, it stops at one of the steps We have to read the errors on the Design Summary panel Once completed, there are no marks next to any one of the steps just performed CS 2204 Spring 2014 Experiment 5 Lab 8 Page 170



Today’s Individual Xilinx Lab Work

18.

Perform a Xilinx IMPLEMENTATION  •     For the current IMPLEMENTATION we will get 0 60 Errors 4% Warnings Slice utilization Read the warnings by clicking on 60 Warnings on the Design Summary window whether or not the Xilinx IMPLEMENTATION completes We often check Design Summary for the warnings FPGA utilization   Most warnings we check are in the Synthesis section and the The FPGA utilization is lower than expected if there are errors or warnings that must be corrected  In Experiment 5, the number of warnings will be 60   This number will change depending on the experiment Note that out of 60 warnings, 58 of them are Synthesis warnings and 2 are Place & Route warnings CS 2204 Spring 2014 Experiment 5 Lab 8 Page 171



Today’s Individual Xilinx Lab Work

18.

Do a Xilinx IMPLEMENTATION

  Make sure there are no errors Always read the warnings !

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 172

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter    Timing simulations are based on delays for the components and signal propogations on the wires Xilinx ISE records these delay only if we perform a Generate

Post-Place & Route Simulation Model

We select this option by expanding the Place & Route step Click here CS 2204 Spring 2014 Experiment 5 Lab 8 Page 173

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter    Timing simulations are based on delays for the components and signal propogations on the wires Xilinx ISE records these delay only if we perform a Generate

Post-Place & Route Simulation Model

Since the Generate Post-Place & Route Simulation Model step has a question mark next to it, we have to perform the step by double clicking on it Double click on this line CS 2204 Spring 2014 Experiment 5 Lab 8 Page 174

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter  When it stops the Generate Post-Place & Route Simulation Model step has a check mark which means we can do timing simulations CS 2204 Spring 2014 Experiment 5 Lab 8 Page 175

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter • Double click here, on the Simulate Post-Place & Route Model step to start the timing simulation CS 2204 Spring 2014 Experiment 5 Lab 8 Page 176

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter • To simulate the counter we need to select its inputs and outputs • • • • We will select one input and five outputs as in the case functional simulations in part (15) We search for in the “Search Results” panel •

Rdclk

and see that a number of results are shown We select the one which is Rdclk We search for

Loadrvc

and see that two results are shown in the “Search Results” panel • We select the one which is Loadrvc We enter RV to select RV3 , RV2 , RV1 • • and RV0 We see that the software lists a number of items related to RV, including the four wires we will select We select RV3, RV2, RV1 and RV0 for our timing simulations !

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 177

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter • To simulate counter we need to select its inputs and outputs Make sure you select the signals as follows : CS 2204 Spring 2014 Experiment 5 Lab 8 Page 178

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter  Click on Restart on the upper tool bar so that the starting time is 0 seconds  Change observation duration time from 1 microseconds to 2 microseconds  Click on the icon to do a simulation for 2 microseconds  The simulator starts with the initial value of 0 • See the next slide that shows the simulation for 20 clock periods CS 2204 Spring 2014 Experiment 5 Lab 8 Page 179



Today’s Individual Xilinx Lab Work

19.

Perform timing simulations on the BCD Up



Counter

In order to simulate the counter, a clock signal must be input to the counter.

 Follow the steps to generate a clock signal as an input • • Enter the following values in the Define Clock window ► ► ► Leading Edge Value is 1 Trailing Edge Value is 0 Period is 100ns After you enter the values the Define Clock window will look like the one on the next slide CS 2204 Spring 2014 Experiment 5 Lab 8 Page 180

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter  In order to simulate the counter, a clock signal must be input to the counter.

 Follow the steps to generate a clock signal as an input • Enter the following values in the Define Clock window CS 2204 Spring 2014 Experiment 5 Lab 8 Page 181



Today’s Individual Xilinx Lab Work

19.

Perform timing simulations on the BCD Up Counter Loadrvc is 1 when the count is 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 The first edge is a positive edge CS 2204 Spring 2014 Experiment 5 Lab 8 Page 182

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter  Zoom into   the leftmost side and determine how long it takes for the It takes 0.645 nanoseconds to change Remember that the • clock period duration is 100ns The counter output change takes place in less than 1% of the clock period duration !

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 183

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter   Zoom into other areas and measure the time delay For example it takes 0.641

nanoseconds for the counter to change its output from  0001 to 0010 Remember again that the • clock period duration is 100ns The counter output change takes place in less than 1% of the clock period duration !

0.641ns

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 184

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter   Zoom into other areas and measure the time delay output from 0111 to 1000 nanoseconds for the counter to change its

0.646ns

Notice the glitch on the loadrvc line CS 2204 Spring 2014 Experiment 5 Lab 8 Page 185

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter   Zoom into other areas and measure the time delay output from 1001 to 0000 nanoseconds for the counter to change its

1.61ns

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 186

 Today’s Individual Xilinx Lab Work 19.

Perform timing simulations on the BCD Up Counter  Click on the icon to continue the simulation for 2 microseconds more  The simulation below shows the values for 40 clock periods Loadrvc is 1 when the count is 9 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 187



Today’s Individual Xilinx Lab Work

20.

Download the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly

 In order to test the circuit fast you can input random digits directly to the machine player     After you play, when the state is 3, leave one of switches SW7 – SW4 on to signal you will input the random digit Use switches value SW3 – SW0 to select a random digit Press push button BTN2 so the machine player starts with the random digit you input Turn off the signaling switch (one of before you press push button BTN3 SW7 to play – SW4 ) CS 2204 Spring 2014 Experiment 5 Lab 8 Page 188



Today’s Individual Xilinx Lab Work

20.

Download

are not

the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly

Play the game and verify that the random values If it the random values are not random looking, inspect your circuit in Block 6 and correct the circuit CS 2204 Spring 2014 Experiment 5 Lab 8 Page 189



Today’s Individual Xilinx Lab Work

20.

Download the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly

   If it does not work, inspect your circuit in Block 6 and correct the circuit If you are sure your Experiment 5 circuit is correct then  Copy your experiment 5 folder from the S drive to your laptop Make sure you refresh your memory about the game rules and how to play the game CS 2204 Spring 2014 Experiment 5 Lab 8 Page 190



Today’s Individual Xilinx Lab Work

21.

Ensure again that all circuits related to Experiment 1 , Experiment 2 , Experiment 3



and Experiment 4

  Including Component labels Well drawn circuits

are complete

22.

Help your partners complete today’s project

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 191



Today’s Individual Xilinx Lab Work

23.

Submit your exp5 project once everyone completes the design    If all the team members have finished the new machine player design, they will decide whose project will be submitted Students will TAs fill out a Term Project Check List handout so that feedback can be given to them by the grading Students will signal to a TA who will copy their project 24.

Develop starting the next playing strategy of your machine player that will be designed lab

CS 2204 Spring 2014 Experiment 5 Lab 8 Page 192



Today’s Individual Xilinx Lab Work

25.

Continue Reading the Term Project handout

  Study and play the other two types of the Ppm game to think more about the our machine player’s strategy Human vs. human : ppmhvsh   • Machine vs. machine : ppmmvsm Think about the playing strategy of the machine player that will be designed Also read slides at the end to learn about the software, Project Manager, Schematic design and other related topics CS 2204 Spring 2014 Experiment 5 Lab 8 Page 193

 Understand Critical Wires RD : 4 bits  The random digit R1D : 4 bits Next random digit R2D : 4 bits  The random digit after next random digit DISP : 16 bits They represent the four position displays  In Hex  DISP15-DISP12 : The leftmost position display, PD3 DISP11-DISP8 : position display PD2, etc  NPDISP : 16 bits  The result of RD to each display digit  In Hex   NPDISP15-NPDISP12 : The leftmost position, PD3, value + RD NPDISP11-NPDISP8 : Position display PD2 value + RD NPSELDISP : 4 bits  Selects one of NPDISP display values  In Hex CS 2204 Spring 2014 Experiment 5 Lab 8 Page 194



Understand Critical Wires

BRWD : 4 bits  Basic reward  In Hex  The digit played and also minimum points earned  It is selected from RD or NPSELDISP  Based on how the player played : Directly or with an addition Brwdeqz : 1 bit    BRWD is zero when it is 1 PDPRD : 4 bits Display overflow bits after addition Pdprd : 1 bit The display overflow bit of the position played Selplyr : 1 bit The current player  If it is 0, it is the human player, otherwise, it is the machine player CS 2204 Spring 2014 Experiment 5 Lab 8 Page 195

 Understand Critical Wires P1SEL : 4 bits         The position played by the human player P2SEL : 4 bits The position played by the machine player PSEL : 4 bits Position Select bits of current player ENCPSEL : 2 bits The number of the position played EQ : 4 bits The equality of the four displays to the digit played NSD : 2 bits The number of similar digits, i.e. the adjacency information of the position played RWD : 8 bits The regular reward points calculated based on adjacencies  In Unsigned Binary CODERWD : 8 bits The code reward points calculated based on the code digits  In Unsigned Binary CS 2204 Spring 2014 Experiment 5 Lab 8 Page 196



Understand Critical Wires

P1PT : 8 bits     Player 1 points  In Hex P2PT : 8 bits Player 2 points  In Hex PT : 8 bits The points of the current player  In Hex NPT : 8 bits New player points for the current player  In Hex Ptovf : 1 bit The points overflow  if it is 1, the new player points is above (255) 10 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 197



Understand Critical Wires

P1add : 1 bit        Player 1 adds when it is 1 P2add : 1 bit Player 2 adds when it is 1 Add : 1 bit The current player adds when it is 1 P1skip : 1 bit Player 1 skips when it is 1 P2skip : 1 bit Player 2 skips when it is 1 P1played : 1 bit Player 1 has played when it is 1 P2played : 1 bit Player 2 has played when it is 1 CS 2204 Spring 2014 Experiment 5 Lab 8 Page 198

 Understand Critical Wires DISPSEL : 2 bit  Selects one of four values for displays  00 Selects position displays (displays that RD is played on)   01 Selects player points 10 Selects next two random digits 11 Selects discovered code digits  Add : 1 bit    Shows that the current player has selected to add Stp1pt : 1 bit Store Player 1 points Stp2pt : 1 bit Store Player 2 points Grd : 1 bit Signals to generate a new random digit  The random digit counter output is stored as P2RD while P2RD and P1RD are shifted to generate the new P1RD and RD Bpds : 1 bit Blink one or all displays slowly Bpdf : 1 bit Blocks a display fast after a display overflow CS 2204 Spring 2014 Experiment 5 Lab 8 Page 199

 Understand Critical   Wires Clear : 1 bit       Clear FFs, registers, counters, etc. during reset in Block 2, Block 4 and Block 6 so that it can play again Clearp2ffs : 1 bit Clears Player 2 FFs, counters and registers Clff : 1 bit Clears FFs in Block 2 so that the next player can play if there is no overflow S1 : 1 bit State 1 where when it is 1, the Ppm is in state 1 P2sturn : 1 bit Signals that Player 2 has the turn  It is 1 when the Ppm is in state 4 Sysclk : 1 bit System clock of the operation diagram at 6 Hz P2clk : 1 bit  The clock signal of Player 2 at 48 Hz Rdclk : 1 bit  The random digit counter clock at 192 Hz CS 2204 Spring 2014 Experiment 5 Lab 8 Page 200