Chapter 7

H. Jonathan Chao Page 1

The Architecture of the Abacus Switch 4/24/2020 H. Jonathan Chao Page 2

The Multicast Grouping Network (MGN) 4/24/2020 H. Jonathan Chao Page 3

Routing Information Used by Abacus Switch with N =256, M =16 4/24/2020 H. Jonathan Chao Page 4

An Example of Modifying A Mulitcast Pattern (MP) 4/24/2020 H. Jonathan Chao Page 5

Implementation of the Input Port Controller (IPC) with N =256, M =16 4/24/2020 H. Jonathan Chao Page 6

On-Off Source Model 4/24/2020 H. Jonathan Chao Page 7

Maximum Throughput versus Group Size, L =1.0

4/24/2020 H. Jonathan Chao Page 8

Maximum Throughput versus Group Expansion Ratio with M =1 4/24/2020 H. Jonathan Chao Page 9

Maximum Throughput versus Group Expansion Ratio with M =16 4/24/2020 H. Jonathan Chao Page 10

Comparison of Average Input Buffer Delay and Average Output Buffer Delay 4/24/2020 H. Jonathan Chao Page 11

Average Input Buffer Delay vs. Expanded Throughput for Unicast and Multicast Traffic (Simulation) 4/24/2020 H. Jonathan Chao Page 12

Input Buffer Overflow Probability versus Output Buffer Size (Simulation) 4/24/2020 H. Jonathan Chao Page 13

Output Buffer Overflow Probability versus Output Buffer Size (Simulation) 4/24/2020 H. Jonathan Chao Page 14

Block Diagram of the ARC Chip 4/24/2020 H. Jonathan Chao Page 15

32x4 SWE Array 4/24/2020 H. Jonathan Chao Page 16

Truth Table for Different Operation Nodes 4/24/2020 H. Jonathan Chao Page 17

Two States of the Switch Element 4/24/2020 H. Jonathan Chao Page 18

Chip Summary 4/24/2020 H. Jonathan Chao Page 19

Photograph of the ARC Chip 4/24/2020 H. Jonathan Chao Page 20

A Two-Stage Memoryless Multi-Stage Concentration Network (MMCN) 4/24/2020 H. Jonathan Chao Page 21

Routing Delay In a Two-Stage MMCN 4/24/2020 H. Jonathan Chao Page 22

The Minimum Value of L for a Given M 4/24/2020 H. Jonathan Chao Page 23

A Two-Stage Buffered Multi-Stage Concentration Network (BMCN) 4/24/2020 H. Jonathan Chao Page 24

Three Ways of Building the Concentration Module (CM) 4/24/2020 H. Jonathan Chao Page 25

An Example of Priority Assignment In the Concentration Module (CM) 4/24/2020 H. Jonathan Chao Page 26

An Example of Cell Out-Of-Sequence with Arbitration Cycle of 3 Cell Slots 4/24/2020 H. Jonathan Chao Page 27

The Maximum Degree of Cell Out-Of-Sequence ( t ) 4/24/2020 H. Jonathan Chao Page 28

Complexity Comparison of Three Approaches for a 160 Gbit/s Abacus Switch 4/24/2020 H. Jonathan Chao Page 29

A Packet Switch with Packet Interleaving 4/24/2020 H. Jonathan Chao Page 30

Delay Performance of A Packet Switch with Packet Interleaving 4/24/2020 H. Jonathan Chao Page 31

A Packet Switch with Cell Interleaving 4/24/2020 H. Jonathan Chao Page 32

Delay Performance of a Packet Switch with Cell Interleaving 4/24/2020 H. Jonathan Chao Page 33