Transcript Document

T0 Electronics Production
Readiness Review
W.H.Trzaska
on behalf of T0 team
HIP, Department of Physics
University of Jyväskylä, Finland
W.H.Trzaska
T0 PRR, February 10, 2006
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Outline
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Introduction
Shoebox amplifier, CFD (Jyväskylä)
VDL (MEPhI)
OR (MEPhI)
Mean Timer (MEPhI)
TVDC (KI; ?)
MPD (KI; ?)
FAN-OUT (KI; ?)
QTC (INR; Tatiana Karavicheva)
T0TU (INR; Tatiana Karavicheva)
NIMLVDS (INR; Tatiana Karavicheva)
Cabling, HV, LV, DCS (Tomasz Malkiewicz)
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T0 PRR, February 10, 2006
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T0-C
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T0-A
Distance to IP
3907mm
3853mm
3746mm
T0-A
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T0 electronics layout
24 PMT
Analog
signals
Shoe-box
Analog signals to TRD
Analog
signals X 2
L1 - L2a - L2r
Fast
Electronics
TTCrx
Busy
FE data
TRM
TRM
Readout data VME
DRM
SIU
Trigger signals
to CTP
W.H.Trzaska
ALICE
Trigger
ALICE DCS
DDL
ALICE
DAQ
ALICE DCS
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Full chain readout test
November 2005
• T0 time and amplitude digitized and stored with
the latest version of TOF hardware (HPTDC)
• HV and laser attenuator under DCS
• CFD DCS prototype tested
• Next round of “full chain” tests scheduled:
– Jan 06 Moscow
– Feb 06 Jyväskylä
– Mar 06 CERN
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T0 PRR, February 10, 2006
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Time resolution of a single PMT channel
At high
multiplicities the
final T0
resolution will be
considerably
better than that of
a single PMT
T0/V0 Shoebox
works very well!
W.H.Trzaska
50
Sigma of time resolution (ps)
Results from
November 2005
full-chain readout
test at CERN
Direct output
10x amplified
40
30
20
10
0
0.1
1.0
10.0
100.0
Amplitude (MIP)
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Shoebox for T0 and V0
• T0 and V0 must provide TRD wake-up
• Wake-up must be generated inside L3
• Need for a box with electronics
– Jyväskylä part to split & amplify pulses
3 mV – 3 V; 0.6 – 600 pC (V.Lyapin)
– Heidelberg part to duplicate trigger logic for
TRD (K. Oyama)
24 PMT
Shoe-box
TTCrx
Fast
Electronics
FE data
TRM
TRM
TRM
Readout data VME
DRM
SIU
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T0 PRR, February 10, 2006
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T0/V0 amplifier
Internal Clamping
V.Lyapin
Va
Input
+
-
V
b
+
-
11.01.06
G=1
G = 10
20 Ohm
+
G = 10
1600
1400
Vb, mV
1200
1000
BFQ81
BFR92
BFT92
BFT93
MMBD1703
BFR520
800
600
400
200
=
0
0
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1000
2000
3000
4000
Va,
T0mV
PRR, February 10, 2006
5000
9
Clamping has no significant effect
on the performance of the amplifier
50
100
45
90
Direct channel without clamping
Direct channel with clamping
80
40
Direct channel without clamping
70
Direct channel with clamping
60
30
Walk (ps)
Resolution (ps)
35
25
50
20
40
15
30
10
20
5
10
0
0
1
10
100
1
100
Amplitude (MIP)
Amplitude (MIP)
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Radiation test
at Jyväskylä in
August 2005
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T0 PRR, February 10, 2006
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LDO Voltage Regulator
UCC284DP-5
(Texas Instrument)
Broken at ~100 krad exposure
20
120
Current (mV)
Gain
Current +6V
Current -6V
100
15
10
5
80
60
40
20
0
0
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50
100
Dose (krad)
150
0
T0 PRR, February 10, 2006
0
50
100
Dose (krad)
150
12
TRDP FEB T0-A/C, V0-A/C-[0..3]
2 x 12 (T0) + 2 x 32 (V0) = 88
88 + 22 spares = 120 total
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Main features
• Based on ultra-wideband current-feedback operational
amplifier OPA695
– max output current 100 mA, 4300V/usec slew rate
– >450MHz bandwidth at higher gains (G = +8) .
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Size – 55 x 55 x 15 mm
Power supply +6 V 0.1A and – 6V 0.1 A
Max power consumption 1.2 W
Input – SMA connector, 50 Ohm impedance
Output 1 – SMA connector gain 1 (“direct output”)
Output 2 – SMA connector, gain 10
Output 3 – 2 pins, differential level analog signal with
gain 10 to TRD discriminator
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T0 PRR, February 10, 2006
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Shoebox amplifier cost estimate
€
Component name
120
units per Ampl.
subTotal
number of units to be made
OPA695
1.10
2
264
UCC284
2.80
1
336
THS4503I
4.00
1
480
TPS7350
1.00
1
120
Resistors
0.04
26
125
Capacitors
0.20
14
336
Electrolytic capac.
4.10
8
3 936
Trimmers
2.10
3
756
BFR520
0.31
1
37
RClamp0502B
0.28
1
34
SMA connectors
8.20
3
2 952
Soldering
15.00
1
1 800
PCB production
35.00
1
4 200
Total [€]
15 376
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Component costs (ampl.)
€
units per Ampl.
subTotal
OPA695
1.10
3
396
UCC284
2.80
1
336
TPS7350
1.00
1
120
Resistors
0.04
26
125
Capacitors
0.20
14
336
Electrolytic capac.
4.10
8
3,936
Trimmers
2.10
3
756
SMA connectors
8.20
3
2,952
Soldering
15.00
1
1,800
PCB production
35.00
1
4,200
Total [€]
14,957
Component name
120
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CLK Distribution
From Shoeboxes
1
...
...
Cable
Delay
Cable
Delay
1
12
13
to TRMs
to NIM units
CLK
14
MPD
MPD
R
24
12
CLK
24
Side C
13
13
1
CLK
...
NIM
LVDS
Analog
NIM CLK
...
LVDS->NIM
Side A
FAN
From Shoeboxes
CPDM
12
24
BC
Delay
1-12
CFD
1-12
(A)
(C)
Mean
Timer
CAN BUS
QTC
1-12
1
12
OR
(C)
(A)
CLK
NIM->LVDS
CLK
TVDC
CLK
CLK
TRMs
CLK
TRMs
(A)
QTC
NIM->LVDS
NIM->LVDS
CLK
(C)
CLK
T0 Trigger Unit
CLK
TRMs
T0v T0A T0msc T0mc T0C
to C T P
TRM
VME Bus DCS
24 PMT
VME Bus DAQ
Shoebox
TTCrx
Fast
Electronics
FE data
TRM
TRM
TRM
Readout data VME
DRM
T0 fast electronics
SIU
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T0 PRR, February 10, 2006
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Canberra CFD – 6 or 12 needed @ 3 k€ per unit
ADDER
DISCRIMINATOR
ZERO
SHAPER
NIM
OUTPUT
ECL-NIM
ANALOG
INPUT
DISCRIMINATOR
CLK
U0
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T0 PRR, February 10, 2006
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Necessary modifications to CFD
(to control Threshold & Walk via DCS)
• Installing SMC sockets
• Changing 2 resistors per channel
– Changing settings by external voltages instead
of a build-in potentiometer
• Tested and works well
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T0 PRR, February 10, 2006
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Canberra CFD 454 modification
Before
After
-5V
10 kOhm
+
100 Ohm
10 kOhm
To Threshold
comparator
1 kOhm
100 Ohm
1 kOhm
To Threshold
comparator
10 kOhm
10 kOhm
10 kOhm
1 kOhm
1 kOhm
Check point
W.H.Trzaska
-5V
Threshold
SMC
connector
Threshold
+
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Canberra 454 CFD
Features
• Four CF discriminators in a single-width NIM
• 200 MHz count rate capability
• 1000:1 dynamic range
• Typical walk <±30 ps for 100:1 dynamic range
• Selectable fraction or leading edge operation
• Output indicator LED
• 6 units needed if only one output per PMT is used
• 12 units if also the non-amplified will be used
• 3 000 € per unit (price in Finland with 0% VAT)
How to purchase electronics?
W.H.Trzaska
T0 PRR, February 10, 2006
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Variable Delay Line (VDL)
Parameters:
1
NIM
ECL
Register
Delay
IN
4
NIM
ECL
ECL
MC10EP195
Code 10 bit
OUT
ECL
MC10EP195
Register
Delay
1
NIM
NIM
4
 Number of independent delay
channels in the single unit: 4.
 Standard of input and output
signals: NIM.
 Signal plug: SMC.
 Step of delay tuning: 10 ps.
 Range of delay tuning: 10 ns.
 Control code: 10 bits.
Code 10 bit
The programmable delay unit is intended mainly for equalizing the signal
delays at the individual channels of PMT before their delivery to the ORA
and ORC circuits. Moreover, the VDL can be used for the choice of initial
delay of TM and TVDC units, and it can be used in all other cases for
precise remote tuning of delay.
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T0 PRR, February 10, 2006
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VDL prototype (24 units needed)
W.H.Trzaska
T0 PRR, February 10, 2006
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Test results of VDL unit
Delay line calibration data.Unity step of the code corresponds to 10 ps
1000
900
800
TDC CHANNEL NUMBER
700
600
500
400
300
200
100
0
0
200
400
600
800
1000
1200
CODE NUMBER
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T0 PRR, February 10, 2006
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Second VDL prototype in VME
standard (24 channels needed)
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T0 PRR, February 10, 2006
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Main features
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Based on MC100EP195
4 independent channels
VME standard 6U (233 x 160)
Power supply – +5V, +12V
Dissipated power – 8 W
4 inputs (1 per 1 channel),NIM standard,
LEMO connectors
• 4 outputs per channel, NIM standard, LEMO
connectors
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T0 PRR, February 10, 2006
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Component costs( 8 units = 6 main + 2spare)
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item
cost USD units per mod.
Integrated circuits
32
Resistors
0.04
65
Capacitors
0.2
32
LEMO connectors (single) 4.6
4
LEMO connectors (double) 19
8
Soldering
66
1
PCB production
160 + 40
1
Mech.unit + L.V.connector 50
1
Spare ICs
200
32
TOTAL
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subtotal
2000
21
50
148
1216
528
400
400
200
4963 USD
T0 PRR, February 10, 2006
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Logical Unit “OR” (two needed)
Parameters:
Gate
2
Gate
. . .
. . .
Input signals
1
&
UV2
F
12
Gate
&
CLK
OR
&
NIM
UV1
12 bit
 Input signals are in NIM
standard with the 10 ns
duration;
 Output signals are in NIM
standards;
 Jitter of the output signal
is not more then 25 ps;
 The unit is controlled by
the 12-bit code.
RG
The logic unit is intended for generation of common signal TOA (or TOC)
using the signal from 12 CFD units (constant fraction discriminators).
Moreover, the logic unit provides the possibility for precise tuning of delays
in each PMT-CFD channel by remote commutation of channels. The time
gating can be also provided with the use of CLK signal.
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T0 PRR, February 10, 2006
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OR prototype
in CAMAC
BC
(clock)
Input
1
Input 2
Gat
e
puls
eSwitch
on\out
&
Gate
&
Gat
e
Input 12
&
OR
Output
(NIM pulses)
Gat
e
Decod
er
VME bus
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T0 PRR, February 10, 2006
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Measured characteristics of the module “OR”
700
B
Linear Fit of Data1_B
Output delay, [ch]
650
600
550
500
0
100
200
300
400
500
Input delay, [ch]
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T0 PRR, February 10, 2006
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Logic module “OR”
• 12 inputs for timing signals from 12 CFDs + delay
• Generates timing and logic signals synchronized to the first
input signal within a 10 ps precision.
• Any input channel can be switched off by corresponding
command coming via VME bus (in case of problems).
• STATUS of the module:
– First prototype tested, non-satisfactory results – large
pick-ups
– New 4-layer PCB ready for production
– Completion of production of the second prototype
expected in May 2006
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T0 PRR, February 10, 2006
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Main features of the module
“OR”
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Based on ICs MC100EL31
Dimensions – VME 6U (233 x 160)
Power supply - +5V,+12V,-5V,-2V
Dissipated power – 20 W
13 inputs in NIM standard (LEMO
connectors)
• 5 outputs in NIM standard (LEMO
connectors)
W.H.Trzaska
T0 PRR, February 10, 2006
32
Component costs (2 modules + 1 spare)
item
cost USD units per mod.
Integrated circuits
44
Transistors
1
36
Resistors
0.04
258
Capacitors
0.2
135
DIN64 connector
1.5
1
LEMO connectors (single) 4.6
18
Soldering
60
1
PCB production
1000
1
Mech.unit + LV connectors 50
1
Spare parts
30
200
subtotal
1545
108
33
81
4.5
250
180
1500
150
TOTAL 4051.5
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Mean Timer
Principle of operation
Center of gravity on the time axis of two signals T0A and T0C
in case of a fixed distance between two arrays of detectors
(T0A + T0C )/2 is independent of the position of the vertex
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T0 PRR, February 10, 2006
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Mean Timer
 Input signals are in NIM standards of 10 ns duration;
 Output signals are in NIM standard;
 Jitter of the output signal is not more then 20 ps;
 The accuracy of timing (time binding to the middle point of time
interval ranging within 3 ns) is < 20 ps.
In 1
UV 1
Sw 1
Sw 2
Current
Generator
F
NIM
Comparator
In 2
W.H.Trzaska
UV 2
C
10...100 pF
T0 PRR, February 10, 2006
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Mean timer
1st prototype
• Generates precision
interaction time that
does not depend on
vertex position
– On-line check of
T0 performance
In1
+V
Io
Io
15 mA
NIM/PECL
Driver
15 mA
Fast
Switch
Fast
Switch
NIM/PECL
Driver
In2
C
12 pF
Fast
comparator
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T0 PRR, February 10, 2006
ECL/NIM
Driver
36
Out
Test results of Mean Timer prototype
(CERN, June 2003)
T0 Mean Timer
500
300
PMT1
Time Shift [ps]
PMT2
Mean Timer
100
Expected
-100
-300
-500
0
W.H.Trzaska
5
10
Distance
T0Relative
PRR, February
10,from
2006Vertex [cm]
15
37
Test results of the second prototype
(with generator, December 2004)
Some small changes in the printed board layout of the
Mean Timer are made for the final design.
W.H.Trzaska
T0 PRR, February 10, 2006
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Main features
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•
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Based on ICs – MC10EL
Dimensions – NIM standard
Two units in one module (one spare)
Power supply – +5V, -5V,+12V
Dissipated power – 1.2 W
2 inputs in NIM standard, LEMO
connectors
• 2 outputs in NIM standard, LEMO
connectors
W.H.Trzaska
T0 PRR, February 10, 2006
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Component costs (2 units = 1 main + 1 spare)
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•
item
cost in USD
Integrated circuits
Resistors
0.04
Capacitors
0.2
LEMO connectors
4.6
Soldering
15
PCB production
100
Mechanics
100
Spare ICs
6
units per mod.
6
44
21
8
1
1
1
subtotal
120
4
8
74
30
100
100
60
TOTAL 496 USD
W.H.Trzaska
T0 PRR, February 10, 2006
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FAN-OUT
W.H.Trzaska
T0 PRR, February 10, 2006
41
FAN-OUT main features
• 4 channels per module
• 3 outputs in each channel
• Max. output amplitude 5V (R=50Ω)
• Rise time 1.8 ns
• Zero-level stability ±0.5 mV
• Power consumption
+5V – 0,24 A;
-5V - 0,12 A;
-12V – 0,2 A.
•MPD module has VME 1U width and 6U height.
W.H.Trzaska
T0 PRR, February 10, 2006
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FAN-OUT single unit cost estimate
W.H.Trzaska
T0 PRR, February 10, 2006
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Time stability of zero level (output 1 channel 1)
2,0
Output Voltage Drift, mV
1,5
1,0
0,5
0,0
-0,5
-1,0
-1,5
-2,0
0
200
400
600
800
1000
1200
Time, min
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T0 PRR, February 10, 2006
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Out 1-1 & Out 2-1 crosstalk after correction
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T0 PRR, February 10, 2006
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TVDC electronic module, generating the trigger signal of
the event’s T0-vertex
W.H.Trzaska
T0 PRR, February 10, 2006
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TVDC diagram
UVR
T0A
DS
To PC
CA
B
BA
U
CCA
UVA
AC
ADC
CS
CLK
BR
Digital
discriminator
A > B1
OR
CCC
UVC
UVC
Register B1
Register B2
A < B2
&
E
UVbr
CC
T0v
C – comparator; UV – univibrator; DS – discharge switch; СС –
coincidence circuit; АС – anticoincidence circuit; CS – charge switch;
BA – buffer amplifier; BR – buffer register; OR – mixer.
W.H.Trzaska
T0 PRR, February 10, 2006
V
M
UV
T0C
S
47
TVDC main features
• range of conversion time
intervals: 2,5 ns(5 ns);
• quantization step: 20 ps (for 8bit conversion);
• dead time of conversion: not
more than 25 ns.
• VME interface based on FPGA
Xilinx® XC95108
Spectrum, characterizing the resolution
of TVDC module
The given parameters obtained with the use of timeamplitude converter and flash ADC with the digital
discriminator for TO-vertex signal generation.
W.H.Trzaska
T0 PRR, February 10, 2006
48
TVDC cost estimation
W.H.Trzaska
T0 PRR, February 10, 2006
49
Input signals to TVDC
W.H.Trzaska
T0 PRR, February 10, 2006
50
Output signals of TVDC
W.H.Trzaska
T0 PRR, February 10, 2006
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Multiplicity Discriminator
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52
MPD diagram
CLK
DAC
I
N
P
U
T
S
1
.
.
.
12
Comparator
1
Comparator
3
Comparator
2
Comparator
4
Analog
Analog
Switch
S
Out 1
W.H.Trzaska
VME
S
VME
NIM
NIM
(SemiCentral)
(Central)
T0 PRR, February 10, 2006
13
.
.
.
24
I
N
P
U
T
S
Out 2
53
MPD main features
• Number of inputs: 24
• Maximum amplitude of the signal at each input: 3 V, minimal duration: 3 ns.
• The output signals at the (Semi-Central and Central outputs are in the NIM
standard with the 10 ns duration.
• The maximum amplitude of the signals at the Out1 and Out2 are: ~3 V.
• Power supply:
 +5V – 0.24A;
 -5V – 1.09A;
 +12V – 0.05A;
 -12V – 0.05A
• MPD module has VME 1U width and 6U height. As the VME decoder is used a
FPGA chip (XILINX XC95108).
W.H.Trzaska
T0 PRR, February 10, 2006
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MPD single unit cost estimate
W.H.Trzaska
T0 PRR, February 10, 2006
55
V.Lyapin 21.03.05
Alternative solution for QTC:
slewing correction in reverse
Measured performance
Our test has confirmed that with TDC
range of 50 ns we get 5% accuracy of
amplitude determination.
In the test Canberra 454 CFD and
LeCroy 4416 B LED were used.
Further improved is possible (if
needed) by using Timing Filter
Amplifier to increase rise time of the
analyzed pulses.
6000
LED-CFD time difference, ps
The time difference between LED and
CFD is proportional to the logarithm
of amplitude.
5000
4000
3000
2000
1000
0
10
100
1000
10000
PMT Output, mV
W.H.Trzaska
T0 PRR, February 10, 2006
56
T0 Milestones
Milestone
planned
expected
636
Electronics PRR
Dec-05
10-Feb-06
637
T0C detector test
Jan-06
Feb-06
638
T0C ready for
installation
T0A ready for
installation
Apr-06
Apr-06
Jul-06
Jul-06
639
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T0 PRR, February 10, 2006
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