Transcript ACQUSITION SYSTEM TPC MPD/NICA

R&D FOR TPC MPD/NICA READOUT
ELECTRONICS
S.Vereschagin,Yu.Zanevsky, F.Levchanovskiy
S.Chernenko, G.Cheremukhina, S.Zaporozhets,
A.Averyanov
Laboratory of High Energy Physics, JINR, Dubna, Russia
Varna, 2013
CONTENS
 Introduction (general characteristics of TPC/MPD, &
readout electronics requirements)
 FEE prototype (FEC-64)
 Main option FEE (FEC-128 & RCU)
 Conclusions
1
General view of the MPD detector
2
TPC/MPD
~110000 readout
channels
beam
12 Readout
chambers
E
beam
Field
cage
3
HV-electrode
~28 KV
Main parameters of the TPC
• Size: 3.4m(length) x 2.8m (diameter);
• Drift gas: 90% Ar+10% Methane CH4 or 90%Ar+10%
•
•
•
•
•
4
CO2;
Drift velocity: 5.5 cm/us(Ar + CH4), 2.3 cm/us (Ar +
CO2);
Length of drift volume: 1.7 m;
Data readout: 2x12 sectors (MWPC, cathode pad readout);
Maximal event rate 5 kHz;
Total number of pads ~ 110000;
Simulation results
Central collision on TPC/MPD @ 9GeV
5
Main parameters of the FEE TPC
 Total number of channels ~ 110000
 Data stream from whole TPC – 5 GB/s
 Low power consumption – less then 100 mW/ch
 Fast optical transfer interface
 Based on ASIC and FPGA
6
Front-End Electronics prototype
FEC-64 channels
 Signal to noise ratio, S/N - 30
 NOISE < 1000e- (С=10-20 pF)
 Dynamic Range - 1000
 Zero suppression
 Buffer (4 / 8 events)
PASA chip
16 channels ASIC
(low noise amplification of ALTRO chip
the signal)
16 channels ASIC
(digitization and signal
processing)
7
FPGA - board control
FTDI USB2.0
(prototype only)
Processing in PASA & ALTRO
- FWHM – 190ns
- Baseline restoration after 1ms:
TP C Si gn al
1
~ 5 % in amplifier / shaper
~ 0.1% in dig. chip
0.8
FWHM ~ 190ns
0.6
D( t )
PASA
0.4
0.2
0
0
50
100
150
200
250
300
350
400
t
ALTRO
- Baseline corrections
- Tail cancellation
8
FEE TESTING
FEE on the TPC prototype
Pulse after amplification
9
FEC-64 testing software
10
Block128diagram
of
FEE
base
ch.
FEC 1
DAQ PC
Switch 1
Group 1
Pad Plane ~4500 ch.
FEC 8
RCU
Trigger
FEC 1
Switch 8
FEC 8
Group 8
11
Slow
control
FEE of RoC general diagram
Slow
Control
system
Trigger System
5 Gb/s
Optical interface
Ethernet
HLT TPC
RCU
FEC
group
FEC
group
Switch
Switch
FEC
group
FEC
group
Switch
FEC
group
12
DAQ
PC
Switch
Switch
TPC/MPD READOUT OUTLINE
 Support high data throughput & maximum parallelization;
 HLT (TPC), online reconstruction & events compression;
 Use GPU NVIDIA for computing trigger decision;
 Like ALICE, ATLAS & CBM experiments;
13
DATA READOUT
Online reconstruction
HLT decision to MPD central trigger
processor
HLT
HLT
TPC
PC 24
From other detectors
14
Permanent Data Storage
Event builder
PC 1
Maximum parallelization
HLT - TPC
ROC 24
TPC
15
FEE
PCI-E 1x
FEE
PCI-E 1x
FEE
PCI-E 1x
PCI-E 8 Gb/s and more
GPU BOARD
ROC 1
TPC
MB-PC
Conclusions:
 Prototype card has been designed
 6 prototype cards has been produced & tasted
 Testing software was developed (LabView & C++)
 Base FEE concept was developed
 FEE design toward final version ongoing
16
I would like to express our gratitude for
the help to
Victor Chepurnov (JINR)
Stepan Razin (JINR)
Alexander Moskovsky (JINR)
Luciano Musa (CERN)
17
Thank you for your attention!
Final version of FEE
Basic version of FEC
Switch node
Readout Control Unit
Choice of FPGA technology
 SRAM, where the programmable switch is controlled by an
SRAM memory cell.
 Flash (or EPROM/EEPROM), where the switch is a floating
gate transistor that can be turned off by injecting charge onto
the floating gate.
 Antifuse, where an electrically programmable switch forms a
low resistance path between two metal layers.