Transcript ECE 353 Lesson Slides

ECE 353
Introduction to
Microprocessor Systems
Week 4
Michael G. Morrow, P.E.
Topics
Data Processing Instructions



Shifter operands
Conditional execution and flags updates
Special cases with PC as destination
Memory Addressing Models and Modes
Memory Allocation

Allocation directives, alignment
ARM7TDMI Load/Store Instructions

Addressing modes
“Complexity is our friend.”
Data Processing Instructions
The data processing instructions all use a
shifter operand


Mnemonic{cond}{S} Rd, Rn, <shifter_operand>
In general, Rd  Rn operation shifter_operand
 The non-destructive instructions will not use a
destination register (Rd).
 Some instructions reverse the operand order
 MOV is a data processing instruction without Rn
Since shifts can be part of any data
processing instruction, there are no
dedicated shift instructions.
MOV Instruction
Syntax

MOV{<cond>}{S} <Rd>, <shifter_operand>
RTL

if (cond is true)
 Rd  shifter_operand
 if((S==1) AND (Rd==R15))

CPSR  SPSR
Flags (if S is appended and Rd is not R15)
31
30
29
cond

N, Z, C (C is based on shifter operand)
28
27
26
25
24
23
22
21
20
0 0 I 1 1 0 1 S
19
18
17
SBZ
16
15
14
13
Rd
12
11
10
9
8
7
6
5
4
3
shifter operand
2
1
0
Shifter Operands
Immediate (I=1)


8-bit value, 4-bit rotate code
Signified by #<number>
Register

No shift
Shifted Register


LSL, LSR, ASR, ROR
Shift count from immediate or register
Rotate Right with Extend

Rotates register right 1 bit through CARRY flag
Conditional Execution and Flags
If a condition is used, the instruction will
only be executed if the condition is true.
Flags are only updated if S is used

Some instructions (B, BL, CMP, CMN, TST,
TEQ, etc.) don’t use S
Using flags and conditions – what does
this do?
MOVS
MOV
MOVEQ
MOVMI
R1,
R0,
R0,
R0,
R1
#1
#0
#-1
Special Cases when Rd is R15
If R15 (PC) is the destination of a data
processing instruction and S is appended
 MOVS
 SUBS



R15, R14 ;return from UNDEF mode
PC, LR, #4 ;return from IRQ/FIQ mode
In addition to the transfer into the PC, the
CPSR is loaded from the current mode’s SPSR.
Flags are not affected.
This behavior is intended to only be used to
return from exception modes.
Do not do this in user or system mode – there
is no SPSR and the results are unpredictable!
Specialized Moves
MVN – move negated


Shifter operand is complemented
Note that this is a 1’s-complement (NOT)
MRS – move CPSR/SPSR to GP register
MSR – move GP register to CPSR/SPSR
Data Processing - Logical
AND – bit-wise AND
BIC – bit clear (bit-wise AND with
complement of shifter operand)
EOR – bit-wise exclusive-OR
ORR – bit-wise inclusive-OR
TEQ – test equivalence (non-destructive
XOR)
TST – test (non-destructive AND)
Data Processing - Arithmetic
ADC – add with carry
ADD – add
CMN – compare negative
CMP – compare
RSB – reverse subtract
RSC – reverse subtract with carry
SBC – subtract with carry
SUB - subtract
Multiply-Accumulate
32x32 multiplies - 32-bit result


MLA – multiply-accumulate
MUL – multiply
32x32 multiplies - 64-bit result




SMLAL – signed long multiply-accumulate
SMULL – signed long multiply
UMLAL – unsigned long multiply-accumulate
UMULL – unsigned long multiply
*MLA* instructions do MAC operation:
Ry (Ra*Rb) + Rc
Memory Addressing Models
Linear Memory Addressing

Instructions/registers can specify the complete address
Segmented Memory Addressing


Instructions/registers do not contain the full address,
just part of it (the offset)
The remainder of the address is furnished by a page
register or a segment register
 There may be multiple segment registers


The full physical address is formed by combining the
segment/page register and the offset from the
instruction/register
Advantages / disadvantages
Memory Addressing Modes
Direct Addressing



The operand address is encoded into the
instruction.
In variable length instructions, the full physical
address can usually be encoded.
In fixed length instructions, usually only the
least significant part of the address can be
encoded
 The remainder of the address can be set to 0 (base
page addressing)
 The remainder of the address can be obtained from
a page register or segment register.
Memory Addressing Modes (cont)
Register Indirect Addressing


The instruction specifies a register that
contains the memory address to access
May also support updating the register as
part of the instruction (auto-increment and
-decrement, pre- or post-, etc.)
Memory Indirect Addressing

A memory location (encoded in the
instruction) contains the address to
transfer to/from
Memory Addressing Modes (cont)
Indexed Addressing


The physical address is calculated from a
constant base address (encoded in the
instruction) and the contents of a register
Typically used for accessing data in arrays
 Base address = array starting address
 Register holds (element index × element size)



If byte array, element size = 1
If halfword array, element size = 2
If word array, element size = 4
 The processor may do the index * element size
calculation automatically
Memory Addressing Modes (cont)
Based Addressing


The physical address is calculated from a base
address contained in a register, plus a
constant offset encoded in the instruction
Typically used for accessing information in
data structures.
 Register holds starting address of structure.
 Offset is distance from the start of the structure to
the desired structure element.
 Code can then access any instance of the structure
just by changing register contents to point to it.
Memory Addressing Modes (cont)
PC-Relative Addressing



The address is computed by adding an offset
value encoded in the instruction to the current
value of the program counter.
In many microprocessors, the PC is not part of
the programmer’s model, so PC-relative
addressing is considered distinct from indexed
or based addressing.
The ARM will use PC-relative addressing to
implement the appearance of direct addressing.
 Distance from the instruction to the label must be
known at assembly-time.
ARM7TDMI Memory Allocation
Memory operands

Stored in little-endian format
Data allocation directives




DCB, DCW, DCD, SPACE, ALIGN
Identifiers and initializers
Constants vs. variables
Arrays and strings
Setting up a data area

Read-write AREAs are all linked into SRAM
Variable naming
ARM7 Memory Addressing Modes
All ARM memory addressing modes use a
base register


Can also have a constant offset or use another
register for the offset
The second register can also be shifted
The apparent ability to use direct
addressing with the ARM will be obtained
by using PC-relative addressing


Will look at how ARM accomplishes this later
The same idea will be used for the ADR
pseudo-instruction
ARM7 Load/Store Instructions
LDR/STR

Load and store a 32-bit register
 Does not matter if signed or unsigned

Address should be word-aligned, or rotated
version of the next lower aligned word is
loaded
LDRB/STRB



Load and store an unsigned byte
On load, the value is sign-extended to 32-bits
Stores only access a single byte of memory
ARM7 Load/Store Addressing
Base register +/- immediate offset


Address = (Rn) +/- offset_12
Syntax: [Rn, +/-#<offset>]
Base register +/- register offset


Address = (Rn) +/- (Rm)
Syntax: [Rn, +/-Rm]
Base register +/- shifted register offset


Address = (Rn) +/- (shifted Rm)
Shift modes with immediate shift count
 LSL, LSR, ASR, ROR, RRX

Syntax: [Rn, +/-Rm, shift_mode #count]
Rn is unaffected by these addressing modes
ARM7 Load/Store Addressing (cont)
Pre-indexed

Rn is updated with the calculated address
 Syntax: [Rn, +/-#<offset>]!
 Syntax: [Rn, +/-Rm]!
 Syntax: [Rn, +/-Rm, shift_mode #count]!
Post-indexed

Rn is used as the transfer address. Then, Rn is
updated with the calculated address
 Syntax: [Rn], +/-#<offset>
 Syntax: [Rn], +/-Rm
 Syntax: [Rn], +/-Rm, shift_mode #count
ARM7 Load/Store Instructions (cont)
LDRSB/LDRSH


Load a signed byte/halfword from memory
Byte/halfword is sign-extended to 32-bits
LDRH/STRH


Load and store an unsigned halfword
On load, the value is zero-padded to 32-bits
The addressing modes are similar to
LDR/STR, but are more restricted



Base +/- offset_8
Base +/- register
Pre-indexed and post-indexed
ARM7 Load/Store Instructions (cont)
SWP – swap
SWPB – swap byte


Swap instructions exchange values between
memory and registers in an atomic operation
These are used to implement semaphores,
mutex’s, and similar inter-process
synchronization structures
ARM7 Load/Store Multiple
LDM/STM load and store multiple registers
to memory in a single instruction


Syntax: LDM{<cond>}<addressing_mode>, <Rn>{!}, <registers>
Addressing mode options
 IA – Increment by 4 After transfer
 IB – Increment by 4 Before transfer
 DA – Decrement by 4 After transfer
 DB – Decrement by 4 Before transfer


Register write-back controlled by “!”
Registers are always written/read from
memory with lowest register number in the
lowest address
ARM7 Memory Pseudo-Instructions
Direct addressing (i.e. LDR R0, my_label)

Encoded as LDR R0, [PC, #±offset]
ADR (i.e. ADR R0, my_label)

Encoded as ADD/SUB R0, PC, #number
LDR – Load register

LDR R0, =(expression)
 If expression is a legal immediate value, encodes as MOV/MVN
 Otherwise, allocates a word to store expression in, then loads
from that word using LDR with PC-relative addressing

LDR R0, =(label)
 Allocates a word to store the label’s address in, then loads that
word using LDR with PC-relative addressing
In-Class Exercise
Create a source code template with a code area and a
data area
Allocate a 100 byte array Bytes in the data area
Create a pointer aBytes to the array in the code area
Declare a halfword variable HwVar in the data area and
initialize to 0xAA55
Create a pointer aHwVar to HwVar in the code area
Use byte transfers to set HwVar to 0xCC33
Copy HwVar into R0 as unsigned and R1 as signed
Store the element’s index into the 1st, 50th, and 100th
elements of the array
If the 50th element of the array is not zero, exchange
the 1st and 100th elements of the array
References MOV instruction LDRB instruction SWAPB
instruction Conditions
Wrapping Up
Reading for next week

Chapter 6, 8
Quiz #1 will be held Thursday, 3/1 at
7:15pm in room TBA.




Coverage will be over modules 1 and 2.
Calculators are not permitted. You may
have a 3x5 card with handwritten notes.
The instruction set documentation will be
provided.
If you have a conflict, please send me the
details by email.
Hungarian Notation
c
uc
i
ui
si
li
n
f
d
s
sz
b
by
ct
p
px
signed character
unsigned character
integer
unsigned integer
short integer
long integer
an integer number where the actual size is irrelevant
float
double
string of characters
string of characters, terminated by a null character
an integer or character used as a boolean value
single byte
an integer being used as a counter or tally
pointer to a structure or general void pointer
pointer to a variable of class x, e.g. pi, pf, pli
ARM7 Condition Codes
Opcode
[31:28]
Mnemonic
extension
Meaning
Condition flag state
0000
EQ
Equal
Z==1
0001
NE
Not equal
Z==0
0010
CS/HS
Carry set / unsigned higher or same
C==1
0011
CC/LO
Carry clear / unsigned lower
C==0
0100
MI
Minus / negative
N==1
0101
PL
Plus / positive or zero
N==0
0110
VS
Overflow
V==1
0111
VC
No overflow
V==0
1000
HI
Unsigned higher
(C==1) AND (Z==0)
1001
LS
Unsigned lower or same
(C==0) OR (Z==1)
1010
GE
Signed greater than or equal
N == V
1011
LT
Signed less than
N != V
1100
GT
Signed greater than
(Z==0) AND (N==V)
1101
LE
Signed less than or equal
(Z==1) OR (N!=V)
1110
AL
Always (unconditional)
Not applicable
1111
(NV)
Never
Obsolete, ARM7TDMI unpredictable
MOV Instruction Reference
Syntax

MOV{<cond>}{S} <Rd>, <shifter_operand>
RTL

if (cond is true)
 Rd  shifter_operand
 if((S==1) AND (Rd==R15))

CPSR  SPSR
Flags (if S used and Rd is not R15)

N, Z, C (C is based on shifter operand)
LDRB Instruction Reference
Syntax

LDRB{<cond>} <Rd>, <addressing_mode>
RTL

if (cond is true)
 Rd[7:0]  memory[memory_address]
 Rd[31:8]  0
 if(writeback)

Rn  end_address
Flags

None
SWPB Instruction Reference
Syntax

SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
RTL

if (cond is true)
 temp  (Rn)
 (Rn)  Rm
 Rd  temp
Flags are not affected
Team ConcepTest
What are the primary functions of an
assembler? What sorts of errors might it
detect?
What are the primary functions of a linker?
What sorts of errors might it detect?