VHDL Training

Introduction

  VHDL is used to:  document circuits   simulate circuits synthesize design descriptions Synthesis is the realization of design descriptions into circuits. In other words, it is the process by which logic circuits are created from design descriptions  This training course covers VHDL for PLD and CPLD synthesis  The course will at times draw upon the concepts of VHDL as a simulation language Cypress Semiconductor 1995 ©

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VHDL Training

VHDL Design Descriptions

 VHDL design descriptions consist of an ENTITY and ARCHITECTURE pair   The ENTITY describes the design I/O The ARCHITECTURE describes the content of the design Cypress Semiconductor 1995 ©

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VHDL Training

The Entity

 A “ BLACK BOX ”  The ENTITY describes the periphery of the black box (the design I/O)

BLACK_BOX rst d[7:0] clk q[7:0] co

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VHDL Training

PORTS

 The Entity ( “ BLACK BOX ” ) has PORTS  PORTS are points of communication • PORTS are often associated with the device pins or I/O ’ s of a component   PORTS are a special class of SIGNAL PORTS have an associated SIGNAL name, MODE, and TYPE Cypress Semiconductor 1995 ©

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VHDL Training

PORT modes

A port ’ s MODE is the direction data is transferred:  IN Data that goes into the entity but not out  OUT Data that goes out of the entity but not in (and is not used internally)  INOUT Data that is bi-directional (goes into and out of the entity)  BUFFER Data that goes out of the entity and is also fed-back internally within the entity Cypress Semiconductor 1995 ©

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VHDL Training



TYPES

VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type)  BIT  a signal of type

bit

that can only take values of '0' or '1'  BIT_VECTOR  a grouping of bits (each bit can take value of '0' or '1') e.g.,

SIGNAL SIGNAL

a:

BIT_VECTOR

(0

TO

b:

BIT_VECTOR

(3 3); -- e.g... ascending range

DOWNTO

0); -- e.g... descending range a <= "0111"; b <= "0101"; This means that: a(0) = '0' a(1) = '1' a(2) = '1' a(3) = '1' b(0) = '1' b(1) = '0' b(2) = '1' b(3) = '0' Cypress Semiconductor 1995 ©

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VHDL Training

TYPES (contd.)



Warp

recognizes two other signal types:  x01z • a signal bit that can take values ‘ x ’ , ‘ 0 ’ , ‘ 1 ’ , or ‘ z ’ • this type is useful for three-state outputs and bi-directional signals  x01z_VECTOR • a grouping of x01z ’ s • assignment is similar to BIT_VECTOR Cypress Semiconductor 1995 ©

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VHDL Training

TYPES (contd.)

   INTEGER • useful as index holders for loops, constants, or generics BOOLEAN • can take values ‘ TRUE ’ or ‘ FALSE ’ ENUMERATED • has user-defined set of possible values example:

TYPE TYPE

states

IS

qit

IS

(start, slow, fast, stop); ( ‘ 0 ’ , ‘ 1 ’ , ‘ z ’ , ‘ x ’ ); Cypress Semiconductor 1995 ©

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VHDL Training

The Entity declaration

 VHDL description of the black box:

ENTITY

black_box

IS PORT

( clk, rst:

IN BIT

; d: q:

END

co: black_box;

IN OUT OUT BIT_VECTOR

(7

BIT_VECTOR

(7

BIT

);

DOWNTO DOWNTO

0); 0);

MODE TYPE BLACK_BOX rst d[7:0] clk q[7:0] co

Cypress Semiconductor 1995 ©

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The Entity: An Example

 Write an entity declaration for the following: Port D is a 12-bit bus, input only Port OE and CLK are each input bits Port AD is a 12-bit, bi-directional bus Port A is a 12-bit bus, output only Port INT is a three-state output Port AS is an output only

my_design d[11:0] oe clk ad[11:0] a[11:0] int as

VHDL Training

Cypress Semiconductor 1995 ©

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VHDL Training

The Entity: Example solution

ENTITY

d: my_design

IS PORT

( oe, clk:

IN IN BIT_VECTOR BIT

; (11

DOWNTO

0); ad: a: int:

INOUT OUT OUT

x01z_VECTOR(11

BIT_VECTOR

x01z; (11

DOWNTO DOWNTO

0); 0);

END

as:

OUT

my_design;

BIT

);

d[11:0] oe clk my_design ad[11:0] a[11:0] int as

Cypress Semiconductor 1995 ©

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VHDL Training

Exercise #1: Entity Declaration

 Write an entity declaration for the following: Port A is a 4-bit bus, input only Port EN, LD and CLK are input only Port W is an output only Port X is a 12-bit bi-directional bus Port Y is an output that is also used internally Port Z is a three-state output

your_design en ld clk a[3:0] w x[11:0] y z

Cypress Semiconductor 1995 ©

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VHDL Training

Exercise #1: Solution

ENTITY

your_design

IS PORT

( clk, ld, en:

IN BIT

; a: w:

IN OUT BIT_VECTOR

(3

DOWNTO

0);

BIT

;

INOUT

x01z_VECTOR(11

BUFFER BIT

;

DOWNTO

0);

OUT

x01z);

END

x: y: z: your_design;

your_design en ld clk a[3:0] w x[11:0] y z

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VHDL Training

The Architecture

 Architectures describe what is in the black box (i.e., the structure or behavior of entities)  Descriptions can be either a combination of  

Structural

descriptions • Instantiations (placements of logic gates - much like in a schematic - and their connections) of building blocks referred to as

components

Behavioral

descriptions • Abstract (or “ high-level ” ) descriptions, e.g.,

IF

a = b

THEN

state <= state5; • Boolean equations, e.g., x <= (a

OR

b)

AND

c; Cypress Semiconductor 1995 ©

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VHDL Training

Entity/Architecture pairs

 Since an

architecture

describes the behavior of an

entity

, they are paired together to form a design, e.g.,

ENTITY

logic

IS PORT

( a,b,c:

IN BIT

; f:

OUT BIT

);

END

logic; a b d

LOGIC

g1

USE WORK

.gatespkg.

ALL

;

ARCHITECTURE SIGNAL

archlogic

OF

d:

BIT

; logic

IS BEGIN

d <= a

AND

b;

Behavioral

g1 : nor2

PORT MAP

(c, d, f);

END

archlogic; c

Structural

f Cypress Semiconductor 1995 ©

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VHDL Training

Example Library Element (nor2)

  Packages found in WARP\lib\common nor2 in WARP\lib\common\gates.vhd

- gates.vhd Schematic support for synthesis.

PACKAGE

gatespkg

IS

...

COMPONENT

NOR2

PORT

( a,b qn );

END COMPONENT

; :

IN BIT

; :

OUT BIT

...

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VHDL Training

Example Library Element (cont.)

...

ENTITY

NOR2

IS PORT

( a,b qn :

IN BIT

; :

OUT BIT

) ;

END

NOR2;

ARCHITECTURE

archNOR2

OF

NOR2

IS BEGIN

qn <= (a

NOR

b);

END

archNOR2; ...

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VHDL Training

Why use behavioral VHDL?

   increased productivity, e.g., a 4-bit comparator a VHDL

behavioral

aeqb <= '1'

WHEN

description: a = b

ELSE

‘ 0 ’ ; a VHDL

structural

description: x1: xnor2

PORT MAP

(a(0), b(0), xnr(0)); x2: xnor2

PORT MAP

(a(1), b(1), xnr(1)); x3: xnor2

PORT MAP

(a(2), b(2), xnr(2)); x4: xnor2

PORT MAP

(a(3), b(3), xnr(3)); eq: or4

PORT MAP

(xnr(0), xnr(1), xnr(2), xnr(3), aeqb); increased portability, i.e., designs are not dependent on a library of vendor or device-specific components more readable design flow Cypress Semiconductor 1995 ©

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VHDL Training

Standard VHDL operators

  Logical - defined for type BIT     AND, NAND OR, NOR XOR, XNOR NOT Relational - defined for types BIT, BIT_VECTOR, INTEGER       = =/ < = > = < > (equal to) (not equal to) (less than) (less than or equal to) (greater than) (greater than or equal to) Cypress Semiconductor 1995 ©

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VHDL Training

Standard VHDL operators (contd.)

  Unary Arithmetic - defined for type INTEGER  (arithmetic negate) Arithmetic - defined for type INTEGER  + (addition)  (subtraction)  Concatenation - defined for types STRING, BIT, BIT_VECTOR  & Cypress Semiconductor 1995 ©

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VHDL Training

Overloaded VHDL operators

 Operators are defined to operate on data objects of specific types  For example, the ‘ + operate on integers ’ operator is defined to  signal a,b,c : integer range 0 to 10; c <= a + b; Operators can be “ overloaded ” objects of other types to operate on data  e.g., the ‘ + ’ operator may be overloaded to operate on bit_vectors and integers  signal b,c : bit_vector(3 downto 0) ; c <= b + 2; Warp provides a library to overload many operators Cypress Semiconductor 1995 ©

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VHDL Training

VHDL semantics

 There are two types of statements (The following is more easily understood in terms of simulation) 

Sequential

• Statements

within a process

are

statements sequential

and evaluate sequentially in terms of simulation 

Concurrent

• Statements

outside of a process

evaluate

concurrently

• Processes are evaluated concurrently (i.e., more than one process can be “ active ” at any given time, and all active processes are evaluated concurrently) Cypress Semiconductor 1995 ©

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VHDL Training

Concurrent statements

 Concurrent statements include:  boolean equations   conditional assignments (i.e., when...else...) instantiations  Examples of concurrent statements: -- Two dashes indicates a comment in VHDL -- Examples of

boolean

equations x <= (a

AND

(

NOT

g <=

NOT

(y

AND

sel1))

OR

sel2); -- Examples of

conditional

(b

AND

assignments sel1); y <= d

WHEN

h <= '0' (sel1 = '1')

ELSE WHEN

(x = '1'

AND

c; sel2 = '0')

ELSE

‘ 1 ’ ; -- Examples of

instantiation

inst: nand2

PORT MAP

(h, g, f); Cypress Semiconductor 1995 ©

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VHDL Training

Sequential statements: The Process

   Processes can be either

active

asleep) or

inactive

(awake or  A

process

is a VHDL construct used for grouping sequential statements Statements within a process are evaluated sequentially in terms of simulation A Process typically has a SENSITIVITY LIST  When a signal in the sensitivity list changes value, the process becomes active  e.g., a process with a clock signal in its sensitivity list becomes active on changes of the clock signal Cypress Semiconductor 1995 ©

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VHDL Training

The Process (contd.)



All

signal assignments occur

at

the END PROCESS statement in terms of simulation time  The Process then becomes inactive Cypress Semiconductor 1995 ©

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VHDL Training

Sequential statements: An Example

 Example of sequential statements within a Process: mux:

PROCESS BEGIN IF

(a, b, s) s = '0'

THEN

x <= a;

ELSE

x <= b;

END IF

;

END PROCESS

mux; s a(3 DOWNTO 0) b(3 DOWNTO 0) x(3 DOWNTO 0)  Note: logic within a process can be registered or combinatorial  Note: the order of the signals in the sensitivity list is unimportant Cypress Semiconductor 1995 ©

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VHDL Training

The Process Sensitivity List

 A Process is invoked when one or more of the signals within the sensitivity list change, e.g.,

ARCHITECTURE BEGIN

archlist nand:

PROCESS BEGIN

(a,b)

OF

list b);

IS END

c <=

NOT END PROCESS

nand; archlist; (a

AND

 Note: the process ‘

nand

’ i.e., whenever signal ‘ a ’ is sensitive to signals or ‘ b ’ inside of the process will be evaluated ‘ a ’ and ‘ b ’ changes value, the statements Cypress Semiconductor 1995 ©

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Signal Assignment in Processes

VHDL Training

s a(3 DOWNTO 0) b(3 DOWNTO 0) en x(3 DOWNTO 0)

ENTITY

mux2ltch

IS PORT

( a, b:

IN BIT_VECTOR

(3

DOWNTO

0); s, en:

IN BIT

;

END

x:

BUFFER BIT_VECTOR

(3

DOWNTO

0)); mux2ltch; Cypress Semiconductor 1995 ©

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VHDL Training

Signal Assignment in Processes: Incorrect solution

 Solution using a process with sequential statements:

ARCHITECTURE

archmux2ltch

OF

mux2ltch

IS SIGNAL BEGIN

c:

BIT_VECTOR

mux:

PROCESS

(s, en) (3

DOWNTO

0);

END BEGIN IF

s = '0'

THEN ELSE

c <= b;

END IF

; x <= (x

AND

(

NOT END PROCESS

mux; archmux2ltch; c <= a; en))

OR

(c

AND

en);  Note: when

en

= ' 1 ' ,

x

is assigned the

previous

value of

c

en s a b c Desired Circuit x Cypress Semiconductor 1995 ©

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VHDL Training

END PROCESS: A correct solution

 Solution using a process with sequential statements and a concurrent signal assignment:

ARCHITECTURE SIGNAL

archmux2ltch c:

BIT_VECTOR OF

(3 mux2ltch

IS DOWNTO

0) ;

BEGIN

mux:

PROCESS

(s)

END BEGIN IF

s = '0'

THEN ELSE

c <= b;

END IF

;

END PROCESS

mux; x <= (x

AND

(

NOT

archmux2ltch; c <= a; en))

OR

(c

AND

en);  Note: when

en

= ' 1 ' ,

x

is assigned the

updated

value of

c

Cypress Semiconductor 1995 ©

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Exercise #2: Architecture Declaration of a Comparator

 The entity declaration is as follows:

ENTITY

compare

IS PORT

( a, b:

IN BIT_VECTOR END

aeqb:

OUT BIT

); compare; (0

TO

3); a(0 TO 3) b(0 TO 3)

VHDL Training

aeqb  Write an architecture that causes

aeqb

when

a

is equal to

b

to be asserted  Multiple solutions exist Cypress Semiconductor 1995 ©

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VHDL Training

Three possible solutions



Concurrent

assignment: statement solution using a

conditional

ARCHITECTURE

archcompare

OF BEGIN

aeqb <= '1'

WHEN

a = b compare

ELSE

‘ 0 ‘ ;

IS END

archcompare; 

Concurrent

equations: statement solution using

boolean

ARCHITECTURE

archcompare

OF BEGIN

aeqb <=

NOT

(

END

(a(0)

XOR

(a(1)

XOR

(a(2)

XOR

(a(3)

XOR

archcompare; b(0))

OR

b(1))

OR

b(2))

OR

b(3))); compare

IS

Cypress Semiconductor 1995 ©

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VHDL Training

Three possible solutions (contd.)

 Solution using a

process

with

sequential

statements:

ARCHITECTURE BEGIN

comp:

PROCESS

archcompare

OF

(a, b)

BEGIN IF

a = b

THEN

aeqb <= '1';

END ELSE

aeqb <= '0';

END IF

;

END PROCESS

comp; archcompare; compare

IS

a(0 TO 3) b(0 TO 3) aeqb Cypress Semiconductor 1995 ©

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