Transcript SEU Tolerance of Different Register Architectures in a 0

The NOnA APD Readout Chip
Tom Zimmerman
Fermilab
May 19, 2006
NOnA Detector Readout Requirements
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Record neutrino signal from detector APDs (APD gain ~ 100, C ~ 10pF)
MIP ~ 25 pe gives 2500e input signal
Need low noise front end (< 200 e)
10 us long beam spill every 2 seconds
Beam spill arrival known to +/- 10 us
Integrate APD signals in 500 ns buckets during a 30 us window
After acquisition, perform Dual Correlated Sampling (DCS) and digitize
to extract pulse height and timing
• LSB ~ 100e, max. input = 100Ke: 10-bit dynamic range
• Measurement resolution required = a few percent
Continuous
reset adjust
Continuous
reset adjust
Integrator
Shaper
32
APDs
Hard reset
Hard reset
Original proposed ASIC
(“Pipeline” version)
Analog pipeline
(64 deep)
Write clock
500 ns
Read clock
~ 5 us
10-bit ADC
(Wilkinson)
Digital
Readout
Output clock
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“Pipeline” version design
(One channel of 32 shown)
FE RST
FE RST
10-bit ADC
Analog pipeline,
64 deep (32 us)
Compare
GAIN
Count
Latch
IN
BW
CK 10
D
Digital
output
Next
Channel
10
Shift
Register
Integrator:
10 mV/fC
Shaper:
programmable
gain, shaping
10
Ramp
Write
Read
CONTROL
LOGIC
Count
Vref
RAMP
GEN.
Previous
Channel
10-BIT
GRAY
COUNTER
Control Section (common to all channels)
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Alternate ASIC configuration (“Mux” version)
• Would also like to detect supernova neutrino signal (capture 10s of seconds)
• Requires near 100% live time (continuous acquisition and digitization)
• Use four 8:1 analog multiplexers with external ADCs. Multiplex and
digitize at 8 X [sample freq.] = 8 X [1/500ns] = 16 MHz. Perform DCS and
additional processing digitally in FPGA
• Risk: coupling to low noise front end from continuous digitize/readout
Continuous
reset adjust
Continuous
reset adjust
32
APDs
8
Shaper
8:1 Mux
8:1 Mux
10-bit
ADC
8:1 Mux
10-bit
ADC
8:1 Mux
10-bit
ADC
8
Hard reset
Quad ADC
10-bit
ADC
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Integrator
S.E. to diff.
output amps
8
10
10
10
FPGA
ASIC
10
Mux clock
Hard reset
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Which approach for NOnA ?
• Baseline approach: “Mux” ASIC with external
ADCs, allowing 100% live time. Required:
ASIC + Quad ADC + FPGA.
• Backup approach: “Pipeline” ASIC, allowing
separate acquire/digitize cycles if necessary.
Required: ASIC + FPGA.
• Prototype ASIC: integrate both approaches on
one chip, giving maximum flexibility for
optimizing the APD readout strategy. Use TSMC
0.25 micron process.
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NOnA prototype ASIC
Mux version
analog output
1 of 4
Analog
Readouts
(8 ch. each)
SHAPER
FE RST
FE RST
S.E.
to
Diff.
APD READOUT CHIP
(One channel of 32 shown)
Enable Pipeline
INTEGRATOR
Pipeline version
digital output
SAMPLING
PIPELINE
(64 deep)
READ
AMP
ADC
ADC
COUNT
COMPARATOR LATCH
Digital
Readout
DATA
OUT
10
Next Ch.
GAIN
IN
BW
CK 10
D
Shift
Register
10
Shift
Data
Clock
MUX1
10
10
Control Section
Count
Ramp
Read
Gain, BW, ...
Write
Vref
Prev. Ch.
MUX1
1
ShiftIn
SRCk
Serial
Program
Register
Prog.
bits
CONTROL
LOGIC
10-BIT
GRAY
COUNTER
RAMP
GEN.
8
ANALOG
MUX
CNTL.
Prog.
bits
ChipReset
RingCk ReadWrite
RampCntl
GrayCk
OutCk
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Integrator
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1 LSB ~ 100e: use 10 mV/fC (CFB = 0.1pF), followed by shaper gain (x2-x10)
500 ns sample time: M1 is PMOS to avoid significant 1/f noise contribution.
M1 (PMOS) source is referred to VDD, not ground.
Where to refer APD capacitance for best PSRR?
If IBIAS is fixed, then Vgs1 is constant, so Vin = VDD. If CAPD grounded:
Vout/VDD = Vout/Vin = CAPD/ CFB = 100 (disaster!!)
• If CAPD is referred to VDD:
VDD CAPD
– Tight input loop (minimizes pickup)
– Vout/VDD = 1 (better!!)
? 10p
Vgs1
M1
Iin
Vin
CFB
0.1p
IBIAS
Vout
10 mV/fC
<<IBIAS
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• But what about CSTRAY to ground (bond pad, bondwire, etc.)? Ruins PSRR.
• Use M2 with Vgs = VDD to generate IBIAS.
Two advantages:
– 1. For a given IBIAS, max. Vgs2 yields min. gm2, lowest M2 noise.
– 2. IBIAS changes with VDD. Now Vin = (VDD)[1 - (gm2/gm1)].
If (CSTRAY/CAPD) = (gm2/gm1), then Vout = 0!! (to 1st order).
• Typically (gm2/gm1) ~ 0.05:
M2 noise contribution ~ 2%
Optimum CSTRAY ~ 0.5pF
• Unavoidable CSTRAY is of order 0.5pF!
• Add small programmable input C to gnd.
• Make IBIAS (M2 width) programmable.
• Tweak for best PSRR!
IBIAS
• Assumes same C’s on all channels.
CSTRAY
VDD CAPD
Iin
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10p
+
M1
Vgs1
Vin
CFB
0.1p
VDD
Vout
M2
Bias current source,
Vgs2 = VDD
<<IBIAS
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Integrator output response to VDD transient
Cin = 15 pF (to VDD) + Cstray (to gnd, programmable)
VDD = 20 mV (externally forced transient)
Integrator outputs for 3 different values of Cstray
Tweak Cstray for best VDD immunity!
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Shaper
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Risetime set by (RinCin), programmable. Not affected by gain setting.
Voltage gain set by (Cin/Cfb), programmable. Not affected by risetime setting.
External adjustment for falltime. Falltime affected by gain setting (Cfb).
Falltime independent of signal magnitude.
Cin
Rin
Vref
(0.3V)
Vin
10p
2 – 48K
Cfb
gain adjust
(x2.2 – x10)
Vout
risetime
adjust
1 – 4.5 pF
8R
“hard” reset
1V range
(0.3-1.3V)
M1
“continuous” reset
R
Vref
5 x M1
falltime
adjust
Vref
110 mV range (0.3-0.41V)
(divider keeps M1 linear)
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Shaper output programmable risetime
16 settings give risetime from 57 ns to 446 ns
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Shaper output programmable gain
8 settings give shaper gain from x2.2 to x10.
No significant effect on risetime.
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Shaper output with finite fall time
Vout = 1200 mV
4 values of Vout:
120, 300, 600, 1200 mV
(normalized)
Vout = 120 mV
(feedback divider gives relatively stable
falltime for different output amplitudes)
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Mux Version: single-ended shaper output
converted to differential output to drive ADC
Single-ended to diff. conversion
R
0.8V
(Vref + 0.5V)
2R
Vout+
(0.75-1.75V)
RCM
Shapers
Mux 1
RCM
R
2R
Vout(1.75-0.75V)
Ch. 1
Ch. 2
common mode
feedback
VDD/2
(1.25V)
Mux 8
Ch. 8
0.3 - 1.3V
(Vref = 0.3V)
Differential gain = 2.
Output common mode stays at VDD/2.
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S.E. to diff. amplifier response for different amplitudes (scaled)
Vout+ (positive amplifier output)
Vout =
30 mV
60 mV
120 mV
240 mV
400 mV
1000 mV
10 ns/div
nominal amp bias
Completely settled in < 40 ns
2X nominal amp bias
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Differential output [(Vout+) – (Vout-)] for max. amplitude (2V)
Cout =
0 pF
10 pF
20 pF
30 pF
400
mV/div
10 ns/div
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Multiplexer readout with VDD transient
Variations at integrator outputs (amplified by shaper) appear at mux output.
VDD = 0.3 mV (from operating the mux).
(1 mV/div)
Tweak Cstray for best integrator immunity!
Optimum Cstray depends on Cin to VDD.
Mux readout for 3 different programmed
values of Cstray.
(10 mV/div)
Ch. 0
1
2
3
4
unbonded
unbonded
channels
channels
bonded channel,
Cin = 15 pF to VDD
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Pipeline Version: 64 deep pipeline +
on-chip multichannel Wilkinson ADC
ADC
READ
AMP
READOUT
Next Ch.
COMPARATOR
LATCH
Shaper
output
CK 10
D
10
10
Shift
Register
SAMPLING
PIPELINE
(64 deep)
(1 channel shown)
10
Vref
Shift
Data
Gray
Count
Ramp
Write
Read
Prev. Ch.
Digitize V = (V2 – V1):
Read amp out
V2
V1
Comparator flips and
latches Gray count
V
Compare Reset
Ramp
V
Gray Counter Clock
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Two digitize options
Digitize
cell 1
cell 1
Digitize
cell 0
Digitize
cell 2
cell 2
cell 0
• Option 1: cell only
Vref
V1 = Read amp reset voltage (Vref) always
V2 = Pipeline cell voltage (Vref + excursion due to shaper output)
The ADC directly digitizes the shaper signal level sampled by each cell of
the pipeline. The signal is always positive with respect to Vref.
• Option 2: DCS
V1 = Pipeline cell (n-1) voltage
V2 = Pipeline cell (n) voltage
Digitize
(1 – 0)
Digitize
(2 – 1)
cell 2
cell 1
cell 0
The ADC digitizes the difference between two neighboring pipeline cell
voltages (dual correlated sampling). Continuous shaper reset should not
be used , since only positive differences can be digitized.
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Two acquire/digitize modes
• Mode 1: Separate acquisition and digitization:
First acquire signals by filling the pipeline, then stop acquisition.
Digitize and readout all pipeline cells.
• Mode 2: Concurrent acquisition and digitization:
Acquisition and digitization occur simultaneously (with latency).
Range or resolution must be sacrificed in order to digitize every
500 ns.
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Progress to date
• The chip is completely functional.
• MUX version: performance is adequate and meets all specs.
• PIPELINE version: only the “Separate acquisition and digitization” mode
has been tested. The on-chip ADC digitizes dual correlated samples as
desired.
• The DCS digitize option was used to measure noise.
• “Concurrent acquisition and digitization” mode not yet studied. Coupling
from digital back end to analog front end???
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Noise Measurements
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Conditions:
Integrator input transistor bias current = 1mA
Shaper rise time constant = 206 ns (hard reset, infinite fall time)
Shaper gain = X10 (integrator + shaper = 100 mV/fC)
Dual correlated sample (t = 1000 ns)
Noise downstream from integrator (shaper + ADC) = 41 electrons
(for shaper gain = 10). Subtract this noise from the measurement
to get only the integrator noise contribution.
Many different variations of input transistor W/L.
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Integrator Noise Measurements • Noise slope measurement is accurate
W/L
DCS noise (e)
880/.32
6e + 8.5e/pF
1200/.32
9e + 7.7e/pF
1540/.32
14e + 7.3e/pF
620/.4
7e + 9.4e/pF
880/.4
5e + 8.4e/pF
1540/.4
19e + 7.5e/pF
620/.6
8e + 9.5e/pF
1540/.6
21e + 7.9e/pF
620/1
23e + 10.2e/pF
1540/1
49e + 8.4e/pF
• Noise intercept not as accurate (stray
wiring C ~ 7pF subtracted out)
Best:
10 pF noise = 87e
20 pF noise = 160e
• The measured noise is lower
than the simulated noise! High
confidence in measurements.
• SVX3 chip noise measurements
with NMOS input transistor
(TSMC 0.25 u) showed “excess”
noise at shorter channel lengths
(used L = 0.8u). PMOS shows
no such behavior – shorter is
better (should have tried L =
0.25u!).
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