Transcript No Slide Title

D
The Online Central
Tracker of D0
Silvia Tentindo Repond
Florida State University at Fermilab
(for the D0 Collaboration)
7th International Conference on Advanced Techniques
and HEP - Como, 15-19 October 2001
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Motivation
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Research
New Physics ! 
New Technology :
( new Tev
new D0
new trigger , CTT )
Discovery
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Contents
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
Overview ( Physics, Tev, D0 )
The New Central Tracker in the D0 Trigger (
CTT ) :
 - description of the D0 Trigger
components ( CTT components in detail )
 - The subDetectors for CTT
 - The Hardware and the Algorithms of
CTT: L1CTT and L2CTT ( L2STT )
 Conclusions
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New Physics : Higgs ! etc
SM
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MSSM
Discovery of Higgs at Tevatron
is constrained by Luminosity:
MH < 107.7 GeV excluded
(LEP)
For :
Run IIa 2fb-1
Run IIb 10 fb1
8 fb-1
- >3 s.d. evidence for MH
< 180 Gev
- >5 s.d. discovery for MH
< 120 Gev
- exclude SM at 95% CL
up to 190 Gev if no Higgs
signal
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The Fermilab Tevatron Collider
Chicago

Booster
CDF
DØ
Tevatron
p source
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Main Injector
(new)
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TeV collider at Fermilab
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Peak Luminosity 10
cm-1s-1( 5X1032 cm-1s-1 )
 Energy at CMS 2Tev
Integrated Luminosity
2fb-1 ( 8[30?]fb-1 )
Bunch crossing time
396 ns (132ns)
Turn-on March 1, 2001
First collisions April 3,
2001
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D0 Run II Detector
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D0 Central Tracker
Silicon Tracker
Fiber Tracker
Forward
Preshower
Solenoid
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Central Preshower
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New D0 for Run II
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Muon System Upgrades  Enhanced Muon Trigger
Excellent Run I Calorimeter  EM and HAD Energy
 2 Tesla Magnetic Field  Momentum
 Scintillating Fiber Tracker  Improved Tracking
 Silicon Microstrip Tracker  Secondary Vertexing
 Preshower Detectors  Enhanced EM Identification
 L1 Central Track Trigger  Selection of Stiff Tracks
 L2 Impact Parameter Trigger  Identification of Long-Lived
Particles
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D0 Detector Performance
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 Tracking Efficiency
- 95% for ||<3

Momentum resolution
– dpT/pT2=0.002
 Vertex reconstruction


primary: =15-30m
secondary: =35m (r-),
Offline
algorithms
80m (r-z)
 Lepton ID acceptance


muons: pT>1.5 GeV/c, ||<2
electrons: pT>1 GeV/c, ||<2.5
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NewPHYSICS ! ….but …
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b Tagging
~ 10 fb
HIGGS Physics
???
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New Trigger ! ! !
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FPGA
Field Programmable Gate Arrays
DSP
Digital Signal Processors
Alpha
Alpha Processors
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The hardware for the new
Trigger
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FPGAs
VME
Bus
Inputs
DSPs
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Alpha Processor
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L3 Cache
Memory
CPU (+fan)
PCI-VME
Bridge
VME Bus
PCI Slots
Data
Switches
Magic
Bus
Main Memory
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PCI-Mbus PIO
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D0 CTT Performance
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+ momentum resolution
+ impact parameter
t tbar
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b bar
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Trigger Requirements for D0RunII
The D0 RunII trigger:
 Must be flexible
 Must be fast
 Must recognize interesting signatures
 Must select one of ~10**6 events
 Must have high efficiency and high
rejection
 Dead time must be reduced to minimal
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Trigger Requirements for D0 RunII
The D0 RunII trigger:
FPGAs,DSPs,Alpha’s
 Is re-programmable
FPGAs
 Does parallel processing
FPGAs
 Uses fast devices
 Uses new algorithms that reliably select
interesting signatures
 These algorithms are sophisticated and able
of high rejection
 Pipelining
Pipeline reduces dead time to minimal
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Run II Trigger System
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100us
3 us
Detector
L1 Trigger
7 MHz
CAL
FPS
CPS
L2 Trigger
5-10 kHz
L1CAL
1000 Hz
L2Cal
L2PS
L1
CTT
CFT
L2CFT
SMT
L2STT
Muon
FPD
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100ms
L1
Muon
Global L2
L3
L2
Muon
L1FPD
L1FW: towers, tracks, correlations
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L2FW:Combined
objects (e, , j)
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Silicon Microstrip Tracker SMT
240 cm
6 Barrels
12 Disks
“F”
4 Disks
“H”
Read-out: SVX-II chips 800.000 channels
Hit resol. 10um, secondary vertex resol. 35um
(r,phi)
; 80um(r,z)
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SMT Barrel
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Central Fiber Tracker
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16.000 channels
Read-out: SVX-II chips
Fast enough for L1
2.6 m scintillation fibers,
VLPC readout + 10m
waveguides
 Mounted on 8 cylinders
20<r<50 cm
 8 alternating axial and
stereo doublets (2deg pitch)




S
A
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Preshower Detectors
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 Central and forward
 16.000 + 8.000 channels
 Extruded triangular
scintillator strips with
embedded WLS fibers
 Axial and ±20° stereo
layers
 Refines position and
energy measurements of
EM showers
 Reduces electron trigger
backgrounds by a factor
of 5
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Level 3 Global Tracker
Real data, Run 2001
Track with 5 fiber tracker hits, 5 3D silicon hits
Relative alignment
of silicon and fiber trackers
verified to 40 m level
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Central Tracker Trigger :
Hardware and Algorithms
L1CTT
(L2CTT)
L2STT
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Level 1 CTT
Axial CFT ( Central Fiber tracker ) and CPS ( central PreShower )
Triggers are integrated :





CFT - uses FPGA electronics to perform tracking in 4 pt bins
- tracks are then matched to clusters
CFT stereo layers are not included
CPS stereo layers are not included
- not used in L1, processed for readout to L2CPS preprocessor
Special boards provide interface to the L2STT preprocessor by distributing
the CFT tracks from the octant geometry of CFT to the sextant geometry
of SMT
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Level 1 CTT (cont.)
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L1 CFT/CPS sends 64 trigger terms to L1 framework, formed from :
- Number of clusters without tracks
- Number of tracks as function of :

Charge

Pt bin

Association , or lack, with a – high or low – threshold
preshower cluster
- Occupancy level of the detector
- Total pt
- Phi sector with highest pt
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CTT Organization showing links to the L1 TM, L2 PreProcessors and L3
AFE
MIX
DFE-
COLCTOC
CFT
Ax. 75
CPS
Ax. 5
BCL3
L3
L3
L3
L3
L3
L3
L3
CTOC
CTOC



40

3

CTOC
CTOC
CTOC
CTOC
CTOC

3

STOV
CTQD
CTQD
L2PS
L2CFT
L2PS
CTQD
L1 T
L2STT
L3
L2STT
L3
L2STT
L3
L2STT
L3
L2STT
L3
L2STT
L3
STSX
STOV
STSX
STOV
STSX
L2PS
L3
CPS
Stereo 20
FPSS
L2FPS L3
FPSS
L2FPS L3
FPTT
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FPSS
LEGEND
L3
L1FPS
L2FPS L3
L2FPS L3
FPSS
FSC LINK
LVDS LINK
LVDS LINK
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L2CFT
L2PS
L2CFT
L2PS
L2CFT
CTQD
STSX
STOV
FPS
L3
STSX
STOV
4
L1CFT /CPS
Ax.
CTTT
STSX
STOV
CFT
Stereo.75
TM
DAUGHTER CARDS Each
filling corresponds to a
different flavor
G LINK
TRANSITION CARDS
Each color corresponds
to a different flavor
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Created by Manuel I. Martin
May. 6, 99
Review October 2001
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DFE DaughterBoard for L1CTT
trigger
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L1CTT Tracking Algorithms
Trigger response for Z ee with 4 min.bias


Find tracks of particles down
to Pt of 1.5 GeV
Tag categories (incl. CPS
info): track, isolated track,
electron, ...
A track example
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L1CTT DFEA Firmware
Finds CFT tracks from CFT doublet hits in 4 Pt bin each with 4 sub-bins; In the lowest bin there
are ~8,000 track equations
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D
L1CTT DFEA Firmware
In each Pt bin, track equations are repre-sented as a two dimensional array 44 wide (phi)
and 8 tall (±4 sub-bins).
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
A
B
F
G
H
In the above array, 8 tracks are found, however, only six tracks are reported as follows:
Track A is reported.
Track B is reported, C is pushed on the stack.
Track D is reported
Track E is reported, G is pushed on the stack, F is Lost.
Track H is reported.
Track G is popped from the stack and reported. Stack is then cleared.
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1
+
–
+
–
+
–
+
–
C
D
E
2
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L2 preprocessor CTT
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as it is at present is L2CFT; will be substituted by L2STT:





receives tracks from L1 CFT
- sorts and possibly truncates the tracks before sending to
Global
Output to Global
- tracks sorted by pt
- tracks sorted by impact parameter
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L2 preprocessor STT
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








L2STT uses custom built hardware, but enters standard L2 system
through the CFT preprocessor to provide a standard interface to
Global
receives tracks from L1 CFT
Receives hits from SMT
Reconstructs clusters and clusters centroids from SMT hits
Associates SMT clusters to CFT tracks ( clusters in roads)
Fits associated clusters into STT tracks
Calculates impact parameter
Sends STT tracks to L2Global
Sends SMT hits ( axial and stereo) to L3


- improves pt resolution
- provides vertex information
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L2STT Hardware Design
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CPU
6
7
8
9
10
11
12
Sector 1
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14
15
16
17
18
Sector 2
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terminator
5
spare
4
terminator
3
spare
spare
2
TFC STC STC STC STC STC FRC STC STC STC STC TFC
spare
spare
1
VBD
20
21
Since most
high-pT
tracks stay
in 30° SMT
sector, 12
STT sectors
are
independent
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L2STT DaughterBoards
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L1CTT
FRC
SMT
preprocess SMT data
find clusters
STC
associate clusters
with L1CTT tracks
L3
TFC
L2CTT
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L2STT Card Flavors
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 fiber road card




 track fit card
receive SCL
fan out L1CTT data
manage L3 buffers
arbitrate VME bus
 silicon trigger card


fit trajectory to hits
 CPU



preprocess SMT data
associate hits with CFT
tracks
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

initialization
downloading
monitoring
resets
 VBD
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TFC
Daughter
Board
of
STT
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L2STT Hit Filtering Algorithm
CFT H layer
 To
optimize trackfinding efficiency, track
purity and execution
time, look for hits in all
four layers but allow
hits in only three out of
four layers
2-mm road
CFT A layer
SMT barrels
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L2STT Track Fit Card
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 Eight
TI DSP processors, each receives 2 CFT hits
and r- SMT clusters in road defined by CFT track
C program on DSP selects clusters closest to road
center at each of 4 layers and performs a
linearized track fit:
b
 (r )   r  0
r
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Central Tracker (L2STT) Performance
 Impact parameter resolution of 35 m includes
 beam spot size (30 m)
 SMT resolution (15 m)
 STT introduces negligible uncertainty to resolution
Queuing simulation predicts average STT latency is
25 s with negligible dead-time
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Conclusions
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The requirements for new Physics
have been addressed by providing a
new Accelerator, a new D0
Detector, and a new Trigger
System. The most advanced
Technology once again has offered
and produced the right tools for
the HEP Physicists of the new
generation to go one step further,
in the path of discovery and
knowledge.
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D
Back to Work ………..and
D0 well ! ! !
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Appendix
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The new role of Software in the
Trigger Hardware
100 ms
“software trigger “(L3) uses
sophisticated algorithms, almost identical
to the offline reconstruction software .
Programmable chips - FPGAs, DSPs and
3 us
alpha preprocessors - ( L1 and L2 ) use
fast versions of such algorithms ( “online 100 us
algorithms”) on reduced sets of digital
information from the detector.
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L2STT SIMULATOR
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SMT
Tsim_l2stt
L1CTT
read SMT hits
calculate clusters
read L1_CFT roads
Tsim_L1stt
preprocess SMT data
usefind
filter
LUT
read CFT tracks
clusters
associate clusters
calculate
clusters in road
order in pt
with L1CTT tracks
send to TFC
order in overlays
make LUTs
L2stt_fitting
read clusters in road
LUT to phys coord
L2stt_util
fit SMT & CFT to track
create LUTs
send to L2CTT
clusters factory
hits in road factory
tracks factory
L2CTT
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L3
L2stt_analyze
create Ntuples
for clusters,
roads and
tracks
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L2STT SIMULATOR - Roads
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 X vs Y display of
Clusters in Roads
 t tbar + 2 min
bias event



T itle:
c lus ter_plot.ps (Port rai t A 4)
Creator:
HIGZ Versi on 1.23/09
Preview:
T his EPS pic ture was not s aved
with a preview i nc luded in i t.
Comment:
T his EPS pic ture wi ll print to a
Pos tScri pt print er, but not to
other t ypes of printers.
blue = CFT tracks hit
green = SMT Cluster
red = Cluster in Road
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D
L1CTT
L2STT Emulator Test vectors
SMT
SMT Test vectors
FRC
Cluster FPGA
preprocess SMT data
find clusters
Clusters test vectors
--------- STC --------associate clusters
Filter FPGA
with L1CTT tracks
Roads&Clusters
Test vectors
FRC Test vectors
STC Test Vectors
TFC
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