Transcript Slide 1

3D FPGA
and Trends of Future Logic Fabric
Zvi Or-Bach
MonolithIC 3D
President & CEO
MonolithIC 3D Inc. Patents Pending
Agenda
 Scaling and the Logic Challenge
 Current FPGAs
 The Third Dimension
 The Architecture Opportunity
 The Technology Opportunity
 The Opportunity for Structured ASIC
 Summary
MonolithIC 3D Inc. Patents Pending
Transistors no Longer Dominate – Metal Interconnections Took Over
MonolithIC 3D Inc. Patents Pending
Interconnects Dominate with Scaling [Source: ITRS]
90nm (2005)
45nm (2010)
22nm (2015)
12nm (2020)
1.6ps
0.8ps
0.4ps
0.2ps
Delay of 1mm long
Interconnect
5x102ps
2x103 ps
1x104 ps
6x104 ps
Ratio
3x102
3x103
4x104
3x105
Transistor Delay
 Transistors keep improving
 Surface scattering, grain boundary scattering and diffusion
barrier degrade RC delay
 Low k helps, but not enough to change trend
MonolithIC 3D Inc. Patents Pending
4
MonolithIC 3D Inc. Patents Pending
Accelerating Mask-Set Cost
Increase of interconnection complexity
Increase in mask complexity
Process (m)
=> More Metal Layers
=> Mask cost increases
2.0 … 0.8 0.6 0.35 0.25 0.18 0.13 0.09
Single Mask
1.5
cost ($K)
1.5 2.5 4.5 7.5 12
40
60
# of Masks
12
12
30
34
Mask Set
cost ($K)
18
18 30 72 150 312 1,000 2,000
12
16
20
MonolithIC 3D Inc. Patents Pending
26
IC Design Costs
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0.35 micron
(feature dimensions vs. cost in $ millions)
Prototype
Validation
Physical
Verification
Architecture
0.25 micron
0.18 micron
0.13 micron
90 nm
Source: International Business Strategies
MonolithIC 3D Inc. Patents Pending
Number of Design Starts is Collapsing
Design Starts
Source: VLSI Research, Inc.
MonolithIC 3D Inc. Patents Pending
20
14
20
12
20
10
20
08
20
06
20
04
20
02
20
00
19
98
19
96
19
94
19
92
45,000
40,000
35,000
30,000
25,000
20,000
15,000
10,000
5,000
0
Semiconductors Market Growth
MonolithIC 3D Inc. Patents Pending
(per Quarter)
MonolithIC 3D Inc. Patents Pending
FPGAs Aren't Substituting ASICs
Total FPGA Market <$5B, Slow Growth Since 2000
FPGA Market
5000
4500
4000
$, Millions
3500
3000
Actel
2500
Altera
2000
Xilinx
1500
1000
500
0
1999
2000
2001
2002
2003
2004
2005
2006
Calendar year
MonolithIC 3D Inc. Patents Pending
2007
2008
2009
2010
The Logic Market Growth
MonolithIC 3D Inc. Patents Pending
FPGA at ~$4B Clearly didn’t Fill the ASIC Gap
FPGA market has barely grown in the last 5 years
 FPGA cost-speed-power make it unattractive for many volume
applications
 FPGA penalty is extremely high *
 Gate Density: 1: 20-40
 Power:
1: 9-12
 Speed:
1: 2-4
 Old Process ASIC is preferable in many applications
 Density ~1:32=> 5 process generations (45nm FPGA ~ 0.25m ASIC)
 => 3-4 gen. older ASIC process (0.13m-0.18m) is more competitive
 => 3-4 gen. older ASIC process fab is fully deprecated and hence cheaper
 ASSP + Software in many cases provide a better alternative
*Ian Kuon and Jonathan Rose, "Measuring the Gap Between FPGAs and ASICs", IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems (TCAD) , Vol. 26, No. 2, pp 203-215, Feb. 2007
MonolithIC 3D Inc. Patents Pending
FPGA Achilles’ Heel – PIC (Programmable
Interconnect) >30x Area vs. Masked Via
SRAM
bit
SRAM FPGA connectivity
elements @ 45 nm
Via connectivity element
@ 45 nm
SRAM
bit
4X
4X
Bidi buffer
Via/AF
Via
Area  4 m2
Ratio to AF  100
.2m
Area: 0.04 m2
SRAM
bit
.2m
TS buffer
4X
Area  2 m2
Ratio to AF  50
SRAM
bit
Pass gate
10X
Pitch - 0.2 m
.2 x .2= 0.04 m2
Area  .5 m2
Ratio to AF  12
Current FPGAs use
primarily pass
transistors with a driver.
Average area ratio of connectivity element >30
MonolithIC 3D Inc. Patents Pending
FPGAs see Diminishing Benefits with Scaling
 Over 90% of FPGA programmable logic area penalty is due to
programmable interconnect (‘PIC’)
 Performance and power penalty are direct result of the area
 Transistor as Programmable Interconnect doesn't scale well
 Scaling bring on “The Tyranny of Interconnects”
 Interconnect needs to increase faster than gate count to keep up (Rent’s
rule)
 ASIC adds metal layers with scaling
 PIC limiting factor is the single layer of diffusion shared with the logic.
=> FPGA moved from LUT4 to LUT6-7 as higher
granularity logic cells reduce interconnections
MonolithIC 3D Inc. Patents Pending
Current 3D FPGA Status
 Tier Logic
 Closed Doors 
 Use TFT to build the Programming RAM on top – 2nd tier
 Suggested cost reduction for high volume by removing the TFT
layers and replacing the PIC with ‘Masked Link’
 Tabula
 3D of a different kind – Time
 Just closed additional round of $100M – we wish them luck
 NuPGA
 Just changed its name to MonolithIC 3D
 Antifuse 3D FPGA Concept.
 On the way to a better FPGA discovered a path for practical
monolithic 3D and shifted its strategy to focus on it.
MonolithIC 3D Inc. Patents Pending
Other non-commercial ideas
 Placing configuration
SRAM at different
strata (Lin, El Gamal,
et al., Stanford 20062007)
 Placing hard blocks
like DSP & user
memory at different
strata (Le, Reda &
Bahar, Brown U.
2009)
RR – Routing Resource
LB – Logic Block
ST – Switch Transistor
(pass gate)
LB-SRAM – LB configuration
memory
RR-SRAM – RR configuration
memory
MonolithIC 3D Inc. Patents Pending
Defect Density
Xilinx 2.5D
MonolithIC 3D Inc. Patents Pending
Altera 3D
MonolithIC 3D Inc. Patents Pending
The Future - 3D IC
1950s
Today
Too many interconnects to manually solder
 interconnect problem
Interconnects dominate performance and
power and diminish scaling advantages
 interconnect problem
Solution: The (2D) integrated circuit
Solution: The 3D integrated circuit
Kilby version:
Connections not integrated
3D with TSV: TSV-3D IC
Connections not integrated
Noyce version
(the monolithic idea):
Connections integrated
Monolithic 3D: Nu-3D IC
Connections integrated
MonolithIC 3D Inc. Patents Pending
20
FPGAs:
The 3D-TSV Solution
MonolithIC 3D Inc. Patents Pending
Current 3D-IC : TSV
MonolithIC 3D Inc. Patents Pending
Reinventing FPGA using 3D-TSV
 Use different dies for:
 Programmable Logic
 Programmable I/O
 Programmable Memory
 Build Reticle Size with Multi-Dice Lines for each
 ~One Mask set with many die/functions size options
 Choice of process node and fabrication processes
MonolithIC 3D Inc. Patents Pending
Traditional FPGA Wafers vs. Continuous Array Wafers
FPGA
chip with
IO
Scribe
lanes
Scribe
lanes
IO “chiclet”
with TSV
prep
Traditional wafer of chips
TSVs
FPGA
Logic-only
chunk
TSV
Continuous Array of Logic at 22nm
Wafer of IO Chiclets at 0.15 m
MonolithIC 3D Inc. Patents Pending
Continuous Array Terrain Allows Defining Custom
Logic Sizes from Same Wafers
Chip
size 9
Chip
size 4
Scribe
lane
Chip
size 20
FPGA
Logic-only
chunk
 Long metal tracks cross scribe lines
 Die edges need to be sealed after cut
 Top wafer prepped for TSVs or micorbumps in standard pattern (“socket”) over logic
chunks
MonolithIC 3D Inc. Patents Pending
Assembling Continuous Array Terrain into
Customized Hybrid Stacks
Standard TSV
pattern
Chip
with
logic
size 9
Chip with TSV
visible
3D Hybrid
stack with
TSVs
TSV
prep
IO
0.15 m
memory
22 nm
SerDes
90 nm
• Chiclets
assembly actually happens prior to wafer
dicing
Chiclets
MonolithIC 3D Inc. Patents Pending
Advantages of 3D-TSV FPGA
 Good Fit for the End User Application with optimal size of
silicon - ~2-5 x cost reduction
 Wide range of technologies and function
 Reduce cost by using low cost old process for I/O
 Increase functionality to match user alternative SC
 Allow integration of additional vendors with their own dies
 Huge reduction of $$$ for masks
MonolithIC 3D Inc. Patents Pending
Future SoC New Logic  15%
MonolithIC 3D Inc. Patents Pending
FPGAs:
The Monolithic 3D Solution
MonolithIC 3D Inc. Patents Pending
3D IC Next Generation – Monolithic 3D
Monolithic 3D vs. TSV
(1:10,000 vertical connectivity ratio)
TSV: TSV-3D IC
Monolithic: Nu-3D IC
Layer Thickness
~50m
50-100nm
Via Diameter
~5m
~50nm
Via Pitch
~10m
~100nm
Limiting Factors
Wafer handling (~5m)
Aspect ratio (<10:1)
Lithography=>
Will keep scaling
Wafer (Die) to Wafer
Alignment
~1m
Layer to Layer Alignment
MonolithIC 3D Inc. Patents Pending
=> Will
keep scaling
Layer Transfer Technology (“Ion-Cut”)
 Defect-free single crystal formed @ <400oC
Oxide
Hydrogen implant
Flip top layer and
Cleave using 400oC
of top layer
bond to bottom layer
anneal or sideways
mechanical force. CMP.
p- Si
Top layer
Oxide
p- Si
Oxide
Bottom layer
p- Si
p- Si
H
Oxide
Oxide
Similar process (bulk-to-bulk) used for manufacturing all
SOI wafers today
MonolithIC 3D Inc. Patents Pending
31
Monolithic 3D with State of the Art Transistors
Uses a novel combination of four ideas
 Gate-Last Process and proper sequence of “Ion-Cut”
 Low Temperature Face-up Layer Transfer
 Repeating Layouts
 Innovative Alignment
MonolithIC 3D Inc. Patents Pending
32
A Gate-Last Process for Cleave and Layer Transfer
NMOS
PMOS
Poly
Oxide
Donor wafer
Fully constructed transistors attached to
each other; no blanket films.
 proprietary methods align top layer atop
bottom layer
Device wafer
MonolithIC 3D Inc. Patents Pending
33
A Gate-Last Process for Cleave and Layer Transfer
Poly
Oxide
Step 1. On donor wafer,
fabricate standard
dummy gates with oxide,
poly-Si
S/D Implant
Step 2: Std Gate-Last
Self-aligned S/D implants
Self-aligned SiGe S/D
High-temp anneal
Salicide/contact etch stop
or faceted S/D
Deposit and polish ILD
ILD
MonolithIC 3D Inc. Patents Pending
CMP to top of
dummy gates
34
A Gate-Last Process for Cleave and Layer Transfer
Step 3.
Implant H for cleaving
H+ Implant Cleave Line
Step 4.
 Bond to temporary carrier wafer
(adhesive or oxide-to-oxide)
Cleave along cut line
CMP to STI
Carrier
STI
CMP to STI
MonolithIC 3D Inc. Patents Pending
35
A Gate-Last Process for Cleave and Layer Transfer
Step 5.
 Low-temp oxide deposition
 Bond to bottom layer
 Remove carrier
Oxide-oxide bond
Remove (etch) dummy
gates, replace with HKMG
Step 6. On transferred layer:
Etch dummy gates
Deposit gate dielectric and electrode
CMP
Etch tier-to-tier vias thru STI
Fabricate BEOL interconnect
MonolithIC 3D Inc. Patents Pending
36
Future Monolithic 3D FPGA
 Multi-Tier Programmable Logic
 Tier 0 – The LUT Array + Local programmable interconnect
 Tier 1 – The Clock distribution Network + programmable power
distribution
 Tier 2 – Short Programmable Interconnect
 Tier 3 – Long Programmable Interconnect
 Reinvented PIC
 Antifuse
 1T Memory cell instead of the 6T
 Flash
 DRAM
…
MonolithIC 3D Inc. Patents Pending
Summary




Interconnects are now dominating all logic devices
Early innovations of 3D FPGA stimulate more ideas
FPGA vendors are moving into 3D (so far 2.5D)
Future FPGAs will utilize 3D technology to Reinvent the
FPGA
 TSV to re-architect the FPGA system
 Monolithic to re-architect the programmable logic fabric
 The Future is in the Third Dimension – 3D
MonolithIC 3D Inc. Patents Pending