Transcript No Slide Title

Delivering Success.
Modeling 32 V Asymmetric LDMOS Using
Aurora and Hspice Level 66
By
Alhan Farhanah, Mohd Shahrul Amran, Albert Victor Kordesch
Device Modeling Department,
SILTERRA Malaysia Sdn. Bhd.
2007
Delivering Success.
Outline




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Aurora and HSPICE Level 66 Background
32V Asymmetric HV MOS Background
Modeling Flow for Asymmetric HV MOS
Results and Discussion
Self Heating Effect in HV MOS
Conclusion
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Aurora and HSPICE Level 66
Background
Delivering Success.
 Aurora
o product of Synopsys Inc for Modeling.
o Beside HSPICE Level 66, Aurora also offers all
types of models that normally offered by other
products.
 Contends for the modeling and SPICE simulation
of digital CMOS, analog and RF circuit that
operates up to 100V.
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Aurora and HSPICE Level 66
Background (cont’d)
Delivering Success.
 HSPICE Level 66 is a proprietary product of
Synopsys.
 HSPICE Level 66 model
o self heating, forward and reverse mode,
asymmetric parasitic, and bias dependent
RDS- based on BSIM4
o primarily targets for LDMOS (Lateral Double
Diffused MOSFET) and EDMOS (Extended Drain
MOSFET) device technologies.
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32V Asymmetric HV MOS Background
(cont’d)
Structure
Delivering Success.
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Modeling Flow For Asymmetric HV MOS
Delivering Success.
Golden Die
Asymmetric Behavior Checking
DC Measurement
AC Measurement
Aurora Extraction
And Optimization
Hspice Simulation
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Modeling Flow For Asymmetric HV MOS
(cont’d)
Asymmetric Behavior Checking
Delivering Success.
 Purpose - check the asymmetric effect of the
transistor.
 Measurement - swapping the bias voltage of source
and drain for each measurement.
 Compare IdVd curve for forward and reverse mode
measurement.
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Modeling Flow For Asymmetric HV MOS
(cont’d)
Asymmetric Behavior Checking
Delivering Success.
Almost similar ID
Long Channel Device
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(W/L=25u/25u)
+++ forward mode
___ reverse mode
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Asymmetric Behavior Checking
Significant
ID
Delivering Success.
decrease
VGS
Short Channel Device
(W/L=25u/4.25u)ESSDERC 2007 MUNICH
+++ forward mode
___ reverse mode
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Modeling Flow For Asymmetric HV MOS
(cont’d)
Delivering Success.
 The results showed that shorter length
device exhibits quite significant Id
decrease for reverse mode measurement
while the long channel device exhibits
almost similar Id curve for both modes of
measurement
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Modeling Flow For Asymmetric HV MOS
(cont’d)
DC Measurement
Delivering Success.
 Measurements:
o
o
o
o
IdVg@low Vdd with different Vb
IdVg@high Vdd with different Vb
IdVd @Vb=0 with different Vg
IdVd @high Vb with different Vg
 Before measuring all the modeling devices, Wide
Width and small Length transistor with different
back biases and different temperatures must be
evaluated first
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Modeling Flow For Asymmetric HV MOS
(cont’d)
CV Measurement
Delivering Success.
 To properly model the effect of asymmetric, the
modeling structure for CV need to be designed with
extra structures compare to symmetric structure.
 All the CV modeling structures need to be separated
into 2 different structures:
o Source design rule
o Drain design rule.
 Thus, the CV measurement for asymmetric transistor is
almost double compare to symmetric transistor.
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Modeling Flow For Asymmetric HV MOS
(cont’d)
Extraction and Optimization
Delivering Success.
 Extraction strategy – almost similar to BSIM4
 The preferred mobility model in Level 66
o MOBMOD=0
 Source and Drain parameters are not equal. e.g
RSW and RDW, RSWMIN and RDWMIN
 Both drain side and source side bias dependence
parameters of LDD resistance can be optimized.
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Modeling Flow For Asymmetric HV MOS
(cont’d)
Extraction and Optimization
Delivering Success.
 There are reverse mode parameters available for
optimization i.e ETA0I, ETABI, DSUBI
o Too many of these parameters are not encouraged.
 Self heating effect can be turned on by setting
SHMOD=1 and RTH0>0.
o Strongly advised to set TSHFLAG=1 during the
optimization - internal approximation of self
heating effect will be used during the optimization.
Hence, the speed of the optimization is
significantly improved. In the final step, the
optimization can be refined by setting TSHFLAG=0.
 When self heating is turned on, the temperature
parameters need to be extracted as much as possible
before we do extraction for saturation region
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parameters.
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Modeling Flow For Asymmetric HV MOS
(cont’d)
Extraction and Optimization
Delivering Success.
 Disadvantages of Level 66 model:
 Slower model evaluation -includes internal nodes
(solver need to be invoked for every bias point)
 There is no reliable way to extract thermal
capacitance. Thus, we need to develop a method to
include thermal time constant in our model.
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Results and Discussion
Delivering Success.
W/L = 25um/25um
+++ Meas
___ Model
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Results and Discussion (cont’d)
Delivering Success.
W/L = 25um/4.25um
+++ Meas
___ Model
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Results and Discussion (cont’d)
Delivering Success.
W/L = 25um/25um
+++ Meas
___ Model
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Results and Discussion (cont’d)
Delivering Success.
W/L = 25um/4.25um
+++ Meas
___ Model
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Idsat (uA/um)
Results and Discussion (cont’d)
Delivering Success.
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Vth (V)
Results and Discussion (cont’d)
Delivering Success.
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Results and Discussion (cont’d)
Delivering Success.
+++ Meas
___ Model
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Results and Discussion (cont’d)
Delivering Success.
+++ Meas
___ Model
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Results and Discussion (cont’d)
Delivering Success.
 In this paper, IdVg and IdVd curves for 25um/25um
and 25um/4.25um have been used to demonstrate
model accuracy.
 The model also correctly simulates self heating
effect
 The model scalability (across W and L) also
showed a good agreement with measurement
data. Less than 5%.
 The accuracy of the AC behavior is excellent. Less
than 1%.
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Self Heating Effect in HV MOSFET
Source
P+
STI
Gate
POLY
HEAT
N+
STI
Delivering Success.
N-DRIFT
Drain
N+
STI
N-DRIFT
HPWELL
P-Sub
If P is moderate(mW), self heating is not severe since
it reach its thermal equilibrium with its environment
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Self Heating Effect in HV MOSFET
(cont’d)
Experimental setup
4.7F
Delivering Success.
VDD
50
VD
VG
Pulse Gen
oscilloscope
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Self Heating Effect in HV MOSFET
(cont’d)
Delivering Success.
VG
VD
Dynamic response of HV NMOS to typical gate pulse
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Self Heating Effect in HV MOSFET (cont’d)
RTH extraction
Delivering Success.
 RTH will be extracted from Aurora by fitting the
data for W=25um and different L.
 set SHMOD=1 and RTH0>0.
 This is to ensure that the RTH can be scaled with
L.
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13.5
Delivering Success.
ID (mA)
13
y = -0.4502Ln(x) + 13.612
12.5
Due to SHE
12
11.5
11
1
10
100
Time (us)
1000
Transient drain-current characteristics of HV
NMOS
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Delivering Success.
2.2
2.0
y = 2.3011e-0.0546x
Delta I D (mA)
1.8
1.6
R*C = 1/0.0546
R*C = 18.32 us
1.4
1.2
1.0
0
2
4
6
8
10
Tim e (us )
Time constant for self heating of HV NMOS
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Self Heating Effect in HV MOSFET (cont’d)
Extracted time constant and CTH
Delivering Success.
 Time constant is extracted from :
y = 2.3011e-0.0546x
where thermal time constant, RTH CTH = 1/0.0546
= 18.32 us
From Aurora extraction RTH = 6.85E-03 mºC/W
Hence the extracted thermal capacitance:
CTH = 18.32us/RTH
= 2.67E-03 (W*sec)/ mºC
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Conclusion
Delivering Success.
 Modeling strategies for 32V asymmetric HV
MOSFET using Aurora and HSPICE level 66 has been
presented
 Model shows:
o Excellent DC IV results for entire DC bias range
o Excellent behavior of junction capacitances
 Model scalability (across W and L) also showed
good agreement with measurement data. Less
than 5%
 Correctly simulate SHE
 Extraction of Thermal resistance and capacitance
by Pulsed gate measurement
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Delivering Success.
Thank You
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