Transcript roth+f14

FIGURES FOR
CHAPTER 14
DERIVATION OF STATE GRAPHS AND
TABLES
This chapter in the book includes:
Objectives
Study Guide
14.1 Design of a Sequence Detector
14.2 More Complex Design Problems
14.3 Guidelines for Construction of State Graphs
14.4 Serial Data Code Conversion
14.5 Alphanumeric State Graph Notation
Programmed Exercises
Problems
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Figure 14-1:
Sequence Detector to be Designed
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Figure 14-2
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Figure 14-3
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Mealy State Graph for
Sequence Detector
Figure 14-4:
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Table 14-1 and Table 14-2
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Section 14.1, p. 396
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Figure 14-5
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Section 14.1, p. 396
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Section 14.1, p. 397
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Moore State Graph for
Sequence Detector
Figure 14-6:
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Table 14-3 and Table 14-4
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Figure 14-7
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state
S0
S1
S2
S3
S4
S5
Figure 14-8
sequence ends in
reset
0 (but not 10)
01
10
1 (but not 01)
100
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state
S0
S1
S2
S3
S4
S5
Figure 14-9
sequence ends in
reset
0 (but not 10)
01
10
1 (but not 01)
100
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Figure 14-10
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state
S0
S1
S2
S3
S4
sequence received
reset or even 1's
odd 1's
even 1's and ends in 0
even 1's and 00 has occurred
00 has occurred and odd 1's
Figure 14-11
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state
S0
S1
S2
S3
S4
S5
input sequences
reset or even 1's
odd 1's
even 1's and ends in 0
even 1's and 00 has occurred
odd 1's and 00 has occurred
odd 1's and ends in 0
Figure 14-12
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state
S0
S1
S2
S3
S4
Figure 14-13:
sequence received
reset
0
1
01 or 10
010 or 100
Partial State Graph for Example 1
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state
S0
S1
S2
S3
S4
S5
S6
Figure 14-14:
sequence received
reset
0
1
01 or 10
010 or 100
2 inputs received, no 1 output is possible
3 inputs received, no 1 output is possible
Complete State Graph for Example 1
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Figure 14-15:
Partial Graphs for Example 2
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Table 14-5 State Descriptions for Example 2
State
S0
S1
S2
S3
S4
S5
S6
S7
Description
No progress on 100
No progress on 010
Progress of 1 on 100
No progress on 010
Progress of 10 on 100 Progress of 0 on 010
No progress on 100
Progress of 0 on 010
Progress of 1 on 100
Progress of 01 on 010
Progress of 0 on 010
Progress of 01 on 010
No progress on 010
010 has never occurred
010 has occurred
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Figure 14-16:
State Graphs for Example 2
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Table 14-6.
Present
State
S0
S1
S2
S3
S4
S5
S6
S7
Next
X=0
S3
S2
S3
S3
S5
S5
S5
S5
State
X=1
S1
S1
S4
S4
S1
S6
S7
S7
Output
X =0
00
00
10
00
01
00
01
00
(Z1Z2)
X=1
00
00
00
00
00
00
00
00
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Example 3, p. 406
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Table 14-7
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Figure 14-17:
State Graph for Example 3
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Figure 14-18:
Serial Data Transmission
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Coding Schemes for
Serial Data Transmission
Figure 14-19:
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Figure 14-20a:
Mealy Circuit for NRZ-to-Manchester Conversion
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Figure 14-20b:
Mealy Circuit for NRZ-to-Manchester Conversion
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Figure 14-20cd:
Mealy Circuit for NRZ-to-Manchester Conversion
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Figure 14-21a:
Moore Circuit for NRZ-to-Manchester Conversion
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Figure 14-21b:
Moore Circuit for
NRZ-to-Manchester
Conversion
(c) State table
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State Graphs with
Variable Names on Arc Labels
Figure 14-22:
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Table 14-8. State Table for Figure 14-22
PS
S0
S1
S2
FR=00
S0
S1
S2
NS
01
S2
S0
S1
10
S1
S2
S0
11
S1
S2
S0
Output
Z1Z2Z3
1 0 0
0 1 0
0 0 1
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