Transcript Paper Report - National Sun Yat

SimTag: Exploiting Tag Bits
Similarity to Improve the Reliability
of the Data Caches
Yun-Chung Yang
Jesung Kim, Soontae Kim, Yebin Lee
2010 DATE(The Design, Automation, and Test in Europe)
2

Abstract

Introduction

Related Work

Proposed Method

Experiment Result

Conclusion
Though tag bits in the data caches are vulnerable
to transient errors, few effort has been made to reduce
their vulnerability. In this paper, we propose to exploit
prevalent same tag bits to improve error protection
capability of the tag bits in the data caches. When data
are fetched from the main memory, it is checked if
adjacent cache lines have the same tag bits as those
of the data fetched. This similarity information is stored
in the data caches as extra bits to be used later. When
an error is detected in the tag bits, the similarity
information is used to recover from the error in the tag
bits. The proposed scheme has small area, energy,
and performance overheads with error protection
coverage of 97.9% on average. In contrast, the
previously proposed In- Cache Replication scheme is
shown to incur large performance and energy
overheads.
3

The idea of this paper come from the figure below.

Because of the transient error of tag bit

False-hit
。Refer cache miss as cache hit.

False-misses
。Make cache hit as cache miss.

Replacement errors
。The above both cause the replacement error.
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Protection
EDC(Error
Detection Code)
ECC(Error
Correction Code)
A Framework for
Correction of Multi-Bit
Soft Errors in L2 Cache
Based on Redundancy[12]
ICR: In-cache replication
for enhancing data cache
reliability[4]
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SEC-DED(Single Error
Correction Double Error
Detection)
Vulnerability analysis of L2
cache elements to single
events upset[6]
This paper

The proposed architecture use four additional
component to implement the SimTag.






STI(Same Tag Information) bits consist three
logic parts



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Shifter
STI Encoder
STI Replace Handler
Error Corrector
Main Controller
A valid bit
A set location bit
Way location bit
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
Shifter



STI encoder

8
Use shifter to access lower and upper cache lines.
Another way – counter base
To generate STI bits, compared the tag bits of cache
miss with tag bits from lower and upper sets.

STI Replacement Handler


Error Corrector


Correct the tag bit when error detected by using STI bits.
Main Controller

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Check STI bits on cache replacement, if the STI bits
points to a replacement, it invalidate the STI valid bit
and generate the new STI bits.
If cache miss or tag bits errors, stalled the pipeline and
signal the additional shifter or counter to access
adjacent sets.
10

Experiment Setup

Error coverage

Performance

Energy consumption
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
XEEMU, an improved Intel Xscale PXA80200
power simulator.

Implement the proposed method and ICR.

Use MiBench for experiment evaluation.
12
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ICR shows lower error coverage.

The average of our scheme is 97.9% while ICR
covers 95.7 at most.

13
The performance of the ICR(in-cache replication),
due to the dead block problem, I can suffer from
significant performance.

Addition energy consumption


Datapath energy consumption

14
Average energy consumption increases is 0.4%.
The proposed method does not increase the datapath
energy consumption.

DRAM energy consumption

15
Due to the dead block of ICR(in-cache replication) in the
main memory. This increase the DRAM energy
consumption. While the proposed method does not use
the main memory.
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
Most of the previous technique focus only data
bits in the data cache.

Faulty tag bits can be simply replaced with
correct tag bit from the adjacent cache line for
error correction.

Our technique shows 97.9% error coverage with
low additional energy consumption.