Transcript PXIe FPSC

Implementation of intelligent data
acquisition system for ITER fast
controllers using RIO devices
M. Ruiz, D.Sanz, R. Castro, J.M. López, J. Vega, E.
Barrera
Universidad Politécnica de Madrid
Asociación Euratom/CIEMAT
7th Workshop on Fusion Data Processing Validation and Analysis
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Outline
• Motivation and objective.
• ITER Fast Controllers:
– HW elements.
– SW elements.
• Methodology.
• Conclusions.
7th Workshop on Fusion Data Processing Validation and Analysis
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Motivation and Objective
• Implement “data analysis” as close as possible to the Data
Acquisition Hardware-> Intelligent DAQ
• Traditional approach-> To Use host CPU to implement data analysis.
• New approaches-> To use FPGA in the DAQ device
– Advantages:
• DAQ functionalities are defined by the user.
• Data analysis is implemented in the FPGA, therefore DAQ
provide features of the signals acquired.
• Simple control loops can be implemented in the FPGA
Hardware. Therefore, we have deterministic applications.
– Disadvantages:
• No floating point available but you can use “fixed point”
algorithms.
• You need to program the FPGA with their specific tools. This
is difficult in general!!!
7th Workshop on Fusion Data Processing Validation and Analysis
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Some interesting points to discuss!!!
• Data analysis applications are infinite and the
implementation possibilities too.
– We need some kind of standardization methods. We have
developed a methodology based in the use of reconfigurable
input/output (RIO) devices .
• There are a lot of hardware platforms available to
implement these applications.
– We have selected PCIe based solutions in PXIe form factor.
• There are a lot software environment to integrate the
solutions.
– We have selected EPICs to provide compliant solutions to ITER
CODAC.
7th Workshop on Fusion Data Processing Validation and Analysis
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Plant System Instrumentation and Control model defined by ITERCODAC
High Performance Networks (HPN)
CODAC Terminal
Time Communication Network (TCN)
Central Interlock
System
Mini-CODAC
Synchronous Data Network (SDN)
Audio/video Network (AVN)
Plant Operation Network (PON)
Central Interlock Network (CIN)
Plant System I&C
Plant Operation Network (PON)
Plant
System
Host
Fast
Controller
Fast
Controller
Signal
Interface
Remote
I/O
COTS
Intelligent
Device
Slow
Controller
Slow
Controller
Interlock
Controller
Remote
I/O
Signal
Interface
Signal
Interface
Actuators and Sensors
7th Workshop on Fusion Data Processing Validation and Analysis
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PXI
Fast controller cubicle
PXIe chassis
PCIe to PXIe
link
CPU/Network/Disks
TCN & Timing card
DAQ device
Connectors
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Fast Controller Hardware Elements
PICMG 1.3
Industrial Computer
Ethernet PON
PCIe
PXIe
chassis
NI-PXI6682-1588
TCN
PXI6259
Multifunction DAQ
RIO
FPGA based DAQ- device
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EPICS software architecture
High Performance Networks (HPN)
Time Communication Network (TCN)
Synchronous Data Network (SDN)
Mini-CODAC
Codac Core
System
Audio/video Network (AVN)
Plant Operation Network (PON)
Channel
Access
Plant System I&C
Plant Operation Network (PON)
Plant
System
Host
Fast
Controller
EPICS
IOC
COTS
Intelligent
Device
Signal
Interface
The
IOC allow to interchange
CODAC Terminal
the information
between
the
Central
Interlock
hardware and theSystem
network
using a standard protocol
(channel access)
Central Interlock Network (CIN)
“IOCs are created
automatically using ITER
CODAC tools”
CODAC CORE SYSTEM
Slow
Controller
Slow
Controller
Interlock
Controller
Remote
I/O
Signal
Interface
Signal
Interface
Actuators and Sensors
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EPICS IOC
Process Variables (PVs)
LAN
Channel Access
The ASYN software
module includes the
code supporting a
specific hardware
ITER is developing
“ASYN modules for
different hardware
elements”
Database
Sequencer
Asyn Device
Support
EPICs IOC
ASYN MODULE
Standard
interface
PCIe
I/O Hardware
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Intelligent DAQ devices
LAN
EPICS
IOC
The ASYN module includes the
code supporting a specific
hardware
ASYN MODULE
PCIe
DATA ANALYSIS is
I/O
implemented in the
hardware in this FPGA
Hardware
The FPGA contains a
specific application
implementing DAQ and
preprocessing
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What are the contributions of this work?
•
Implementation of the NIRIO EPICS device support to connect the FPGA
resources with ITER CODAC CORE SYSTEM applications.
– The implementation of a device support following ASYN methodology in EPICS is
not easy. If we are going to implemented multiple solutions in the FPGA, for
instance
• data analysis
• data processing
• spectral estimation.
• data reduction
• Compression
• pattern recognition
• Filtering
• image processing, etc
we cannot implement specific device support for each application. We need a
<<standard>> device support.
– We have created a set of rules to standardize this and we have built this
general purpose “device support” for RIO devices.
– The rules must be taken into account in the implementation of the FPGA
code.
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What is the contribution of this work?
• Implementation of the FPGA code supporting data acquisition and
preprocessing for your specific application
– We have simplified the process using LabVIEW for FPGA
• We have created LabVIEW code patterns for
o Continuous data acquisition + processing single sample oriented
o Continuous data acquisition + processing waveform (block)
oriented
o Single event data acquisition + processing
o Images data acquisition using camera-link interface.
o Customized triggers
o IEEE 1588 time-stamping for samples and blocks (using the PXI6682)
o Waveform (pattern) generation (periodic signals)
o Digital input-output.
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What is the contribution of this work?
• Implement the interface for EPICS to integrate
your solution in ITER CODAC CORE SYSTEM.
– NIRIO EPICS ASYN Device Support implemented
– The device support searches for the resources available in the
FPGA design
– The device support automatically connects FPGA resources and
EPICS records.
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FPGA code implementation using “coreDAQ” pattern (block oriented)
Indicators
InitDone
Controls
NCHperDMATtoHOST
DAQStartStop
SamplingRate0
Fref
DAQStartStop
ADC
Ch[0-N]
SamplingRate0
FPGAVIversion
GroupEnable0
NoOfWFGen
Hardware Logic
ExpexctedIOModuleID
GroupEnable0
RIOAdapterCorrect
FIFO0
DevQualityStatus
DeviceTemp
DMAsOverflow
DATA
PROCESSING
7th Workshop on Fusion Data Processing Validation and Analysis
DMATtoHOST0
DMA PCI/PCIe to
CPU
HOST (DMA)
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Development cycle using CODAC CORE SYSTEM
List of the maximum numbers
elements
of each RIO device
-AI,AO,DI,DO, etc
5
1
SDD
Plant System
I&C developer
SDD Developer
New data base for RIO in
Fast Controllers
IOC unit
3
+
CORE DAQ
Design Rules
m-myUnit
+
=
src
CORE DAQ List of the maximum
Scientist
Design Rules numbers elements requirements
of each RIO device
-AI,AO,DI,DO, etc
2
m-nirio
This package
is installed
like an EPICS
Module in
CCS
projectname.lvbitx
main
projectname.h
epics
resources
Plant System
I&C developer
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4
SDD
Editor
SDD
translator
nirio
bitfile
headerfile
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Steps for implementing “intelligent data acquisition applications
• Select one RIO device and an adapter module
• Develop the FPGA code using LabVIEW for FPGA
– Test the application!!
– The output is a bitfile for programming the FPGA
• Download of resource files to the Fast Controller
Host
• Create and IOC following ITER Codac Core
System Application Manual
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Some results obtained
• Continuous data acquisition moving the data to EPICS:
– Up to 6MS/s using 2 analog input channel (16 bits) in PXI (PCI)
modules (24 MB/s)
– Up to 2MS/s using 32 analog input channel (16 bits) in PXIe
(PCIe) modules (200MB/s)
• Single triggered data acquisition
– Up to 100MS/s using 2 channels.
• Data Analysis and Pattern Recognition
– Real Time Plasma Disruptions Detection in JET Implemented
With the ITMS Platform Using FPGA Based IDAQ (IEEE TNS
Volume: 58 Issue:4 pp: 1576 - 1581 )
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Conclusions
• The methodology for integrating data analysis
applications in RIO devices has been developed.
• The methodology solves the integration of these
applications in ITER fast controllers using EPICS
and CODAC CORE SYSTEM tools.
• The FPGA processing capabilities are limited (if
we compare them with CPUs or GPUs) therefore
new methods like “peer to peer comunications”
among FPGAs should be explored
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Implementation of intelligent data
acquisition system for ITER fast
controllers using RIO devices
M. Ruiz, D.Sanz, R. Castro, J.M. López, J. Vega, E.
Barrera
Universidad Politécnica de Madrid
Asociación Euratom/CIEMAT
7th Workshop on Fusion Data Processing Validation and Analysis
Page 19