Transcript DC Bias 2

Collector Feedback Bias
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BJT Biasing 4
For the Collector Feedback Bias Configuration:
• Draw Equivalent Input circuit
• Draw Equivalent Output circuit
• Write necessary KVL and KCL Equations
• Determine the Quiescent Operating Point
– Graphical Solution using Loadlines
– Computational Analysis
• Design and test design using a computer simulation
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DC Bias with Collector (Voltage) Feedback
Another way to improve the stability of a bias circuit is to add a feedback path
from collector to base
In this bias circuit the Q-point is only slightly dependent on the transistor 
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Base – Emitter Loop Solve for IE
Applying Kirchoff’s voltage law: -VCC + IERC + IBRB + VBE + IERE = 0
Since IE = ( + 1) IB then:
RB
-VCC + IE RC + IE
Simplifying and solving for IE: IE =
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( + 1)
VCC - VBE
+ VBE + IERE = 0
RB
+ (RC + RE)
(β + 1)
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Collector Emitter Loop
Applying Kirchoff’s voltage law:
Since IC = IE and IE = ( + 1) IB:
Solving for VCE:
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IE RE + VCE + ICRC – VCC = 0
IE(RC + RE) + VCE – VCC =0
VCE = VCC – IE (RE + RC)
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Network Example
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Network Example
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Collector Feedback with RE = 0
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Design of CE Amplifier with Collector Feedback Bias
1.
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6.
Select a value for VCC
Determine the value of  from spec sheet or family of curves
Select a value for IEQ
Let VCE = ½ VCC (typical operation, 0.4 VCC ≤ VC ≤ 0.6 VCC )
Let VE = 0.1 VCC (for good operation, 0.1 VCC ≤ VE ≤ 0.2 VCC )
Calculate RE, RC and RB
.1VCC
IE
VCC - VCQ
VCC - .6VCC
.4VCC
RC =
=
; RC =
IE
IE
IE
VCC - IERC - VBE - IERE
VCC - IE (RC + RE) - 0.7V
RB =
;
RB =
IE
IE
β +1
β +1
VE = .1VCC
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RE =
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