Transcript ESDG Group Meeting

Delay FPGA
I/O
Clock 40
4
Clock40
Reset
delay_ser_out
delay_ser_in
busy
ADC_Data_stream_0
10
5
1
1
1
ADC_Data_stream_0
Delay
FPGA
ADC_Data_stream_3
10
Configuration
Multi function
Non I/O pins
Configuration
Bank Drive Voltages
Core Voltage, gnd
Rutherford Appleton Laboratory
Instrumentation Department
5 ADC_Data_stream_3
Bank DCI Resistors
Bank Ref Voltages
Design I/O Total = 73+
2 TEMP SENSE - NF
JTAG
Electronic System Design Group
XC2V40CS144 - 88 I/O
XC2V80FG144 - 92 I/O
R. Halsall, S. Taghavirad et al
5 March 2003
Delay FPGA
Function
4 phases
XC2V40-CS144
CLOCK OUT 0
CLOCK - 40 MHz
DCM 0
IOB
IOB
5 Slices
5 Slices
REG
DCI
10
1
REG
SHIFT
REG
REG
DATA OUT 0
REG
BLOCK RAM 0
10 Slices
DPM
Counter
2.5/3.3V I/O?
4 phases
1.5/1.8/2.5/3.3V I/O?
CLOCK OUT 3
DCM 3
IOB
IOB
5 Slices
5 Slices
REG
DCI
10
4
10
REG
SHIFT
REG
REG
DATA OUT 3
REG
BLOCK RAM 3
10 Slices
DPM
Control
Counter
Clock
Rutherford Appleton Laboratory
RESET
Serial In
CONTROL
Serial Out
busy
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
CMS Tracker FED Firmware
Front End FPGA I/O
Clock 40
3
adc enables
18
Opto Rx
6
Clock40 LVDS
Frame_Sync_out
Frame_Sync_In
2 x Temp Sense8
4
DAC Serial
delay_ser_out
delay_ser_in
busy
ADC_Data_stream_0
3
3
3
Readout_Sync_out
Readout_Sync_In
Front End
FPGA
Config_out (Config_Monitor_Out)
Config_In (Config_Monitor_In)
Monitor_in (DCM Reset)
Monitor_out (Synch Reset)
FE - BE I/O
12 signals
5
4 Data_stream
ADC_Data_stream_11
5
Configuration
3 Full Flags
Bank DCI Resistors
VBatt
Bank Voltages
Power down
JTAG
Core Voltage
Temp Sense
Rutherford Appleton Laboratory
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
CALICE Firmware
Front End FPGA I/O
Clock 40
3
Clock40
adc control x
dac control x
Temp monitor
Frame_Sync_out
Frame_Sync_In (Trigger)
Readout_Sync_out
Readout_Sync_In
LVDS I/O
ADC_Data_stream_0
Front End
FPGA
Config_out (Config_Monitor_Out)
Config_In (Config_Monitor_In)
Monitor_in (DCM Reset)
Monitor_out (Synch Reset)
FE - BE I/O
12 signals
1
4 Data_stream
ADC_Data_stream_11
1
Configuration
3 Full Flags
Bank DCI Resistors
VBatt
Bank Voltages
Power down
JTAG
Core Voltage
Temp Sense
Rutherford Appleton Laboratory
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
CMS Tracker FED FPGA Firmware
Back End FPGA I/O
Frame_Sync_out0
Frame_Sync_in 0
Clock40
DCM Reset
Readout_Sync_out0
Sync Reset
DCM Reset out 0
12
Serial
3
Readout_Sync_In0
FE0
2
Load_Monitor_In 0
control
1 interrupt
Load_monitor_out 0
4
6 spare
VME 32 VME SLINK
Data_stream0
TTCrx
TTS
TTC/S
Spare & Test Trig
Single ended DCI
Frame_Sync_out 7
Frame_Sync_in 7
64
SLINK
Readout_Sync_out 7
SLINK64
Control
J0
4 pairs
J0
3 pairs
J2
32 + 13 pairs
Readout_Sync_In 7
12
Sync Reset
DCM Reset out 7
FE7
Load_monitor_In 7
Load_monitor_out 7
4
LVDS
ef, pf & ff
Rutherford Appleton Laboratory
18 ADDR/CNTRL
QDR
SSRAM
18 DATA IN
x2 QDR Common Address
18 DATA OUT
Data_stream 7
8 x 2 Clock40
Full flags
Bank DCI Resistors
3
Temp Flag
‘I2C’
Bank Voltages
Core Voltage
Instrumentation Department
Temp Sense diode
LM82
BSCAN
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
CMS Tracker FED FPGA Firmware
Back End FPGA Overview
x1
x2
x8
Clock40 VME
Clock
Management
Clock40 TTC
Clock40 J0
Clock40 FE
Channel Link
640 MHz
8
3
Frame_Syncs
SLINK LVDS
Control
SLINK
Serial I/O
interrupt
spare
32
VME
VME SLINK
6
3
Data
64
8
8x
8
Synch/DCM Reset
FF/PF Flags
8
8
CONTROL
2 x 18
64
Data Out
160 MHz
QDR
Load_monitor
Front End
8
Readout_Syncs
2
QDR SSRAM
x2/x4 burst
8x Lengths, Pointers
9
TTS
Data_stream 0
18+4
160MHz
Address
Pipelined Data Mux
2 x 18
64
4
Rutherford Appleton Laboratory
Pipelined
Address Generator
FF, PF, busy
4
160 MHz
Data_stream 7
Fill/run/freeze
Control
Data
TTX
TTC Rx
80 MHz
Instrumentation Department
Electronic System Design Group
Data In
160 MHz
R. Halsall, S. Taghavirad et al
5 March 2003
Load_Monitor 0..7
Serial
Interface
SLINK
Header
Control
VME Serial I/O
P2p Serial
CMS Tracker FED FPGA Firmware
Back End FPGA Control Block
Load_Monitor 0..7
FS in 0..7
FS out 0..7
RS in 0..7
RS out 0..7
Data tap 0..X
SLINK Data 0..63
TTC 0..9
Frame Sync
Interface
Readout Sync
Interface
QDR ADDR/CTRL
Header
Generation
SLINK
QDR Addr
SLINK
SLINK-VME
QDR Data
TTC
Interface
DIagnostics
FE FPGA FF/PF 0..1
TTS 0..X
Flow Control
Interface
Resets
Rutherford Appleton Laboratory
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
CMS Tracker FED FPGA Firmware
Back End FPGA Control Block
FS in 0..7
FIFO
512x80
Serial
Detect
Compare
Rutherford Appleton Laboratory
CTRL
fs_strobe, status= good, some header errors, arrival time error, fatal error
reset, freeze
HEADER
fs_fifo_empty, fs_fifo_full, fifo_data=median header+status
8x Serial Data, markers & control data
DPM
1K
circular buffer
VME SERIAL
CSR
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
Readout Sync
RS in 0..7
CTRL BUS
rs_strobe, status= good, arrival time error, fatal error
reset, freeze,readout_next
Address Gen
Total_length_fifo_empty, total_length_fifo_full, fifo_data= total length
RS out 0..7
FIFO
1K
Serial
Detect
Rutherford Appleton Laboratory
FIFO
8K
fifo_data= 8x sub_lengths
FIFO
8K
fifo_data= 8x pointer_offsets
FIFO
8K
HEADER
copy_fifo_empty, copy_fifo_full, fifo_data= sub_lengths
8x Serial Data, markers & control data
DPM
1K
circular buffer
Instrumentation Department
VME Serial
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
Flow Control core
VME soft reset
Addr Gen FIFO FF
Internal FIFO FF
Internal Freeze
Latch
FE FPGA FF
Addr Gen FIFO PF
Internal FIFO PF
TTS ERROR
TTS BUSY
FE FPGA PF
Addr GEN FF
Internal FIFO EF
Addr GEN Controls
RS Controls
Fill
Flow Control
Fill event
Internal Freeze
SLINK CTRL Busy
Addr GEN EF
Addr GEN Busy
Simplest flow control;
Empty
Flow Control
Internal Freeze
Rutherford Appleton Laboratory
Diagnostic
Event Logger
Halt on any buffer full
Busy on any buffer partially full
Readout event
Circular Buffers
Serial
Time stamped
Control Registers
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
TTC Interface
CTRL BUS
TTC 0..9
ttc_strobe
reset, freeze
Bx,Ex
FIFO
1K
TTC
Interface
Rutherford Appleton Laboratory
Em Hdr
Header
FIFO
1K
DPM
1K
VME Serial
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
VME FPGA
Temp Sensor
EEPROM
I2C
Temp
Sense
CSR
Address/control
System
ACE
SYS ACE
XTAL
J0
Rutherford Appleton Laboratory
VME
INT
data
Clock
Management
BE FPGA Serial
BE FPGA Parallel
Int
32
Clock 40
Serial I/O
control
wait
burst
data
6 spare
BE FPGA
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
VME-BE-Parallel
data
wait
burst
SLINK Data from BE FPGA
DPM
1K
32
VME-SLINK
Interface
‘VME’ BUS
lengths
FIFO
1K
QDR Event Data moved in blocks into DPM
Burst transfer over VME
Wait on software handshake before continuing
Double buffered
Rutherford Appleton Laboratory
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
Rutherford Appleton Laboratory
VME-BE-Serial
DPM
1K
Serial in 0..7
Serial out 0..7
Serial
I/O
Engine
Output
‘VME’ BUS
DPM
1K
Input
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
CMS Tracker FED
System Timing
Frame Sync In
256+12
#2234
Header
ADC Output
Data
Frame Sync
Median header+
Status Message
Frame Sync Out
Accept/abort
Handshake Message
Frame Sync In
#2233
Readout Sync Out
Processed Message
Readout Sync In
#2220 Next/delete
#2221
Readout Message
Readout Message
#2219
Data
Length
Data Burst
#2220
#2221
Data Burst
Data Burst
NB Frame Sync In - Abort/Accept not used, auto accepts. Readout Sync In - delete not used.
Rutherford Appleton Laboratory
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003
CMS Tracker FED
Back End FPGA
#FFFFF
Event N+1
Event N+1
Event N+1
Write Ptr 7
Write Ptr 7
FE 7
Write Ptr 7
Write Ptr 2
Event N
Write Ptr 2
Write Ptr 2
FE 1
Write Ptr 1
Write Ptr 1
Write Ptr 1
Write Ptr 0
FE 0
Write Ptr 0
Write Ptr 0
Read Ptr
Event N-1
Event N-1
Read Ptr
Event N-1
Read Ptr
#00000
Rutherford Appleton Laboratory
T0
Instrumentation Department
T1
Electronic System Design Group
T2
R. Halsall, S. Taghavirad et al
5 March 2003
CMS Tracker FED - Back End FPGA
Floorplan
Die
Package
SLINK
FE_FPGA_Inputs
VME
QDR
Same frame 456 & 676 ?
Clocks
Rutherford Appleton Laboratory
XC2V1000FG456 - 324 I/O
XC2V1500FG676 - 396 I/O
XC2V2000FG676 - 456 I/O
XC2V3000FG676 - 484 I/O
Instrumentation Department
Electronic System Design Group
R. Halsall, S. Taghavirad et al
5 March 2003