Transcript HP_TmpIt_Extened_final

Manufacturability and
Computability at the
Nano-Scale
Frontiers of Extreme Computing
Stan Williams
October 25, 2005
© 2004 Hewlett-Packard Development Company, L.P.
The information contained herein is subject to change without notice
"The purpose of QSR is to perform
fundamental research in physical science
with a strategic intent for hp
– to create new technologies that will be
important to the company on a
10+ year time frame."
Discover + Invent
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For a more detailed discussion of this work, see
Applied Physics A 80, March 2005
“Nanoelectronics” Special Issue
Journal of Applied Physics 97, #034301 (2005)
2005 WSJ Technology Innovation Award
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Fabrication by Nanoimprint
Gun-Young Jung
Inkyu Park (Intern)
Wei Wu
Zhaoning Yu
William Tong
S.-Y. Wang
Hylke Wiersma
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QSR Hyper Moore’s Law Progress
16 k
1k
2005
64
2004
1
2003
2002
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Lithography Red Brick Wall - 2010
QSR > 13 years ahead!
International Technology Roadmap for Semiconductors 2004
year
04
05
06
07
08
09
10
11
12
13
14
15
16
17
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DRAM
90
80
70
65
57
50
45
40
35
32
28
25
22
20
18
½ pitch
nm
30 nm
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17 nm
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G4 nanoimprinter: Total cost $300k
1st
NIL
2nd
NIL
10 mm
Wei Wu
•Much more cost-effective than any commercial nanoimprinter
•0.5 mm alignment accuracy demonstrated
•Targeting 10 nm alignment accuracy (with J. Gao & C. Picciotto)
•Step & repeat compatible design
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Architecture
Phil Kuekes
Greg Snider
Warren Robinett
+ITR
Gadiel Seroussi
Ronnie Roth
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Tunneling-Switch
Address
Crossbar
Circuits
lines
US Patents 6128214, 6256767, 6314019
Memory
1
Switch
Data
lines
Abstraction of a Field-Programmable Gate Array
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Switchable Tunneling Resistor
Ti
Device =
Molecule
+ Electrodes
Current (mA)
Pt
10
Switch off
"0"
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0
Switch on
"1"
-5
-10
Read bit
-2.0
-1.0
0.0
Voltage (V)
1.0
(measure
resistance)
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Communicate with the nanowires
selected
column
k-bit
address
memory grid
selected
row
selected
memory
cell
k-bit
address
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row
selector
(demux)
column
selector
(demux)
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Use coding theory to design circuits!
•
Protecting messages
Noise
corrupted
estimate of
codeword
message
message
codeword
Encoder Y Channel Y' Decoder
A
A'
A
k bits
n bits
n bits
k bits
Defects
message
A
k bits
codeword
Encoder U
n bits
Protecting calculations?
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Decoder 0
Decoder 1
Decoder 2k-2
output
S
2k bits
Decoder 2k-1
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Four kbit Cross Bar Memory with
Mux/Demux
66x66 cross bar
memory @30 nm
half-pitch
Address lines
Mux/demux
*Mux/demux propramming done by E-beam burning
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No Gain,
No Logic?
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RESTORE
& INVERT
ENABLE
1
Controls (V)
SW1
C1
2
Clock /
control
C1
C2
SET 1
SET 2
RESET
TUNNELING SWITCH LATCH: EXPT DATA
SW2
E
0
-1
1
C2
0
D
Data
input
Q
Data
out
-1
-2
200
SW1
Data (V)
0.5
SW2
0
Test 1
input +0.5V
out -0.46V
-0.25
100
-0.5
Test 2
input -0.5V
out +0.50V
0.5
0
0
Data (V)
Current (uA)
500
0.25
-500
-100
-1
0
Voltage (V)
1
0.25
0
-0.25
-1
0
Voltage (V)
1
-0.5
0
Duncan Stewart
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4
6
8
Time (s)
10
12
15
Expt: Latch works!
Voltage (V)
0.5
0.4
Trial 1
0.3
3
0.2
5
Signal restoration
Inversion, if desired
>100mV operating margin
0.1
0.0
-0.1
-0.2
6
-0.3
4
-0.4
2
No nanoscale transistor!
-0.5
Input
Output
J. Appl. Phys. Feb 1, 2005
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The Tunneling-Switch Latch Provides
Logical State Storage
Signal Restoration
Signal Inversion (Logical NOT)
(with no need for a nanoscale transistor)
Universal Computation!
(Finite State Machine with wired ANDs and ORs)
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Area comparison of NAND gates
CMOS NAND gate
Area = 36×(FP)2
= 1.2m2 @ 90 nm hp
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SIMPL NAND gate
Area = 3×(FP)2
= 0.01m2 @ 30 nm hp
No VDD, no static power!
Low dynamic power
Register and Logic
Permute inputs and outputs
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1 x 17 Latch and Logic Array
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Experimentally measured NAND truth table –
Output on Rpull down measured at indicated Step #
VA
VC
VB
Output
Rpull down
Driving
Junction A
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Receiving
Junction
Driving
Junction B
Junction A
Junction B
Rpull down
Step #
0
0
1
10
0
1
1
19
1
1
0
28
1
0
1
37
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Experimental V vs. t data for NAND demonstration
NAND Function tristate drive, Location 41x, 39y, sweep 2
10
5
8
4
Junction 4,5,6 voltaages [V]
1
1
3
4
2
2
1
0
0
0
5
10
15
20
25
0
30
35
-2
-1
Junction 4
-4
Junction 5
Junction 6
-6
Output
-8
-2
-3
-4
Time [sec]
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Output [V]
1
6
Summary of Serial Implication Logic
•
SIMPL is simple!
•
Tunneling switches  state machines.
•
Linear array + demux; high density.
•
State encoded with impedance, not voltage.
•
No static power dissipation.
•
Nonvolatile.
•
Conditional copy with inversion is ‘implication’
•
Compiler construction completed.
•
nanoCircuits built and currently under test.
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