Transcript cs.kennesaw.edu

VLIW & ILP
Mohini Patel
Juan Roach
Alyssa Cohen
Javier Duque
ILP
ILP- Instruction Level Parallelism
● executes multiple operations in parallel
● speed up execution
Two strategies to support ILP
● Dynamic Scheduling: relies on the hardware
● Static Scheduling: relies on the software
Superscalar
●
Superscalar is another technique that
implements ILP
●
Executes more than one instruction in
different parts of the processor every
clock cycle
○
Must not have dependencies
Pipelining
●
●
Pipelining is a form of parallelism.
Components of instructions sent to the
CPU
o FETCH
o DECODE
o EXECUTE
o WRITE-BACK
ILP Architecture
Sequential Architectures
Dependence Architectures
Independence Architectures
VLIW
VLIW is an architecture that attempts to achieve
high levels of instruction parallelism by executing
long instruction words.
Long instruction words are instructions that
specify several different and independent
operations.
Fixed number of operations are bundled together
as a “very long word instruction”.
Each instruction is created by a compiler.
VLIW Implementation
And Advantages
● Relies on software (compiler) to
create instructions.
● VLIW relies on software rather
than hardware.
● Trace-driven compilation.
First compilation
Second compilation
● VLIW processor’s registers are
general purpose rather than
specific.
● Better performance
● Reduced power consumption
VLIW Example
● IA-64 EPIC
o 128 bit bundles with 3 instructions per bundle
o Full predicted execution
● Example of execution:
cmp.eq r1, r2, p1, p2
(p1) sub 59, r10, r11
(p2) add r5, r6, r7
References
http://www.hpl.hp.com/techreports/92/HPL-92-132.pdf
http://visl.technion.ac.il/documents/trimedia/vliw-wp.pdf
http://courses.cs.washington.edu/courses/csep548/06au/lectures/vLIW.pdf