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Transcript real-time embedded systems
Interrupt Controller and Edge Port in Coldfire
Computer Science & Engineering Department
Arizona State University
Tempe, AZ 85287
Dr. Yann-Hang Lee
[email protected]
(480) 727-7507
7/23
Interrupt Controller in Coldfire Processor
in Coldfire core
256 entries in vector table
0-63 exceptions and 64-255 user-defined interrupts
IPL in Status Register
Expect a vector number during IACK cycle
interrupt (3 bits)
Peripheral
1
IACK
vector
Coldfire core
clear interrupt
interrupt
configuration
and status
Interrupt
controller
Peripheral
2
Peripheral
3
set 7 -- 1
Interrupt Controller
Each of 63 interrupt sources
source number (vector), interrupt level, priority within a level,
mask, and pending status
Interrupt level 1-7 compared against IPL in SR
if greater, CPU is interrupted
9 priorities in each level
Interrupt source 1–7 (from the edgeport module) is hardwired to
the given level and represents the mid-point of the priority within
the level.
Interrupt controller
Recognition
Prioritization – sends 3-bit encoded interrupt priority level to CPU
Vector determination during IACK
set 7 -- 2
Interrupt Controller Registers
Pending register(IPRH, IPRL)
63 bits for sources 63-1
1 for active request, 0 for no request
Mask register (IMRH, IMRL)
1 for disable request, 0 for enable
Force register (INTFRCH, INTFRCL)
write 1 to generate an interrupt from a source
Interrupt control resgisters (ICR01-ICR63)
to define interrupt level and priority for each source
IACK register (SWIACK, L1IACK-L7IACK)
vector number of the highest priority interrupt for each level
set 7 -- 3
A Spurious Interrupt
May occur if an interrupt source is being masked in IMR while
the interrupt mask in the status register (SR[I]) is set to a
value lower than the interrupt’s level.
If an interrupt arrives and, by the time that the status register
acknowledges this interrupt, the interrupt has been masked.
Cannot determine the interrupt source.
To avoid this situation for interrupts sources with levels 1–6,
write a higher level interrupt mask to the status register,
then set the mask in the IMR.
return the interrupt mask in the status register to its previous value.
Since level 7 interrupts cannot be disabled in the status
register prior to masking, use of the IMR to disable level
seven interrupts is not recommended.
set 7 -- 4
Example: SW1 Interrupt
/* add ISR to vector table */
mcf5xxx_set_handler(64 + 4, sw1_handler);
/* Enable IRQ signals on the port */
MCF_GPIO_PNQPAR = 0
| MCF_GPIO_PNQPAR_IRQ4_IRQ4;
/* Set EPORT to look for rising edges */
MCF_EPORT_EPPAR = 0
| MCF_EPORT_EPPAR_EPPA4_RISING;
/* Enable interrupt from EPORT */
MCF_EPORT_EPIER = 0
| MCF_EPORT_EPIER_EPIE4;
/* Enable interrupts in the interrupt controller */
MCF_INTC_IMRL &= ~(0
| MCF_INTC_IMRL_MASK4);
set 7 -- 5
Edge Port
Seven external interrupt pins, IRQ7–IRQ1.
as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising
edge, falling edge, or both), or a general-purpose I/O pin.
default to general-purpose input pins at reset.
set 7 -- 6
Edge Port Control
Pin assignment register (EPPAR)
00 Pin IRQx level-sensitive
01 Pin IRQx rising edge triggered
10 Pin IRQx falling edge triggered
11 Pin IRQx both falling edge and rising edge triggered
Data direction register (EPDDR).
Interrupt enable register (EPIER)—enables interrupt requests for
each pin.
Data register (EPDR)—holds the data to be driven to the pins if
configured as GP output pins.
Pin data register (EPPDR)—reflects the current state of the pins.
Flag register (EPFR)—individually latches EPORT edge events.
set 7 -- 7