Transcript Power Integrity: A Nanoscale VLSI Challenge

Power Integrity: A Nanoscale
VLSI Challenge
Raj Nair, Anasim Corporation
Oct. 2, 2008
Overview
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Scaling & its less-known L*di/dt challenge
The Power Wall, breaking through
True-Electromagnetic PI analysis
Energy & Noise Management
Non-disruptive Scaling
Summary
October 2008
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Scaling Progression
October 2008
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Planar CMOS transistor Scaling
Gate
Delay  1
Freq  1
1
1
Tox
Source
L
Body
Drain
1
Gate
0.7 Tox
Source
0.7 L
Body
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Drain
0.49
0.7
Delay  0.7
1
Freq 
 1.43
0. 7
A lower Energy*Delay*Cost
product… but challenges led to a
0.7
© 2008AnaSIM severe Power Wall
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Scaling Challenge: CPU Chip PI
Transistors double
every ~18
months
Power doubles
every ~36
months
Operating modes
create load
shifts
Which create
supply voltage
‘droops’
Microprocessor
Heat Spreader
Package Managed by
Substrate package
Mother Board
Capacitors
(Original
figure from C. Baldwin)
devices
Pentium™ is a trademark of Intel® Corporation
October 2008
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Package CAP Loop-L scaling
Load shift induced voltage noise
equation and derivation of package
component characteristics scaling
gives
and
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loop-L, pH
Inversely related to
process scaling
(on-die cap) &
(freq. scaling)2
Quintuplet and Triplet loop-L scaling
1
0.1
Q-scaling
References:
0.01
Nair
P858
2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’
2002 Intel Technology Journal paper “Emerging Directions for Packaging…”
October 2008
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T-scaling
<<0.1pH!
P860
P1262
Process
P1264
65nm
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On-die L & L*di/dt challenge
Consider a Roots of Two Scaling [1] scenario:
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Capacitance-per-unit-area, Ca, scales by 2 , operating voltage scales by
1
, frequency
2
scales by 2 , and chip area scales by
1
2
.
Following this constant-power scaling direction, and inspecting the change in Dynamic Voltage Droop
in a unit area (/ua) of integrated silicon, we get:

Since C/ua scales by
2 and voltage scales by
1
, I scales by
2* 2.
2
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Assuming the effective L/ua doesn't change,
Multiplying I and

I
L
reduces by a factor of
C
1
.
2
L
in the scaled process generation, the dynamic voltage droop amplitude:
C
L
scales by
C
2* 2*
1
, or by a factor of
2
for constant power scaling.
2
References:
Nair, Nair & Bennett, 2008
EDADesignline® publications “A Power Integrity Wall follows the Power Wall” & “Dynamic Voltage Droops & Total PI”
October 2008
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The Power Wall
Processor power doubles
every ~36 months…
Pentium™
processors
Power (Watts)
100
1
486
286
10
8086
8085
8080
386
8008
4004
0.1
’71
’74
’78
’85
’92
’00
’04
’08
CPU power is now capped or reducing
in Multi-Core, SoC Architectures
References:
Nair
2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’
2002 Intel Technology Journal paper “Emerging Directions for Packaging…”
October 2008
© 2008AnaSIM
Pentium™ is a trademark of Intel® Corporation
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Scaling into the Nanoscale Era
Drain induced barrier lowering in short
channel devices makes leakage increase
with Vds (V-Supply)
Source:
Narendra & Chandrakasan
Leakage in Nanometer Technologies, Springer Publications, 2005
October 2008
Sub-threshold channel leakage dominates
V-supply dependent leakage.
Greater challenges…
High-K is only a partial solution
© 2008AnaSIM
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Power, Performance, Leakage
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Power
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Active power estimated as
(P=CV2f), V  P
With supply-V scaling, VT
must scale for performance
Leakage
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IOFF  10е(VT/S), and S
~= 85mV/decade
IOFF rises 10X with 85mV
reduction in VT
Short channel barrier
lowering (DIBL, )  IOFF 
Source: S. Narendra, Tyfone, Inc.
October 2008
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Power Trend
54%
42%
18%
4%
0%
0%
0%
Power trend
15
Present
10
Switching
Leakage
Total
5
0
1.4X
Sub-threshold
leakage
0.01
0.1
1
Channel length (um)
Leakage power now equals active power!!
Both strongly dependent upon supply voltage.
Reference: Narendra, ICCAD ‘03
October 2008
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Performance w/ Voltage Scaling
IDS  (VGSVT)
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15nm
Delay & Frequency
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Linear dependence in
deep nanoscale CMOS
CVdd/Ids ~constant
Nanoscale CMOS delay
and performance are
roughly constant within
a ΔVdd range of Vdd
Opportunity
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Use lowest possible Vdd!
500
Vg = 0.8V
Intel’s 15nm NMOS
m A/ m m)
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25 nm
Drain Current (
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400
0.7V
300
0.6V
200
0.5V
0.4V
100
0.3V
0
Accurate supply noise estimation
a must
© 2008AnaSIM
October 2008
0
0.2
0.4
0.6
0.8
Drain Voltage (V)
Chau et al., IEDM 2000
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}
}
}
Voltage Minimization is Key
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Total power strongly V-dependent
Active power proportional to V2
 Leakage (tunneling) also related as Vx (DIBL, Efield, tunneling distance reduction with V)
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Energy / task minimized similarly
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ΔIDS ~linearly related to ΔV in nanoscale processes
How low can you go?
Digital: supply gating
 Analog: fine grain supply voltage control
 Need accurate noise, power integrity estimation
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Reference: Nair, AZ Nanotechnology Symposium 2006
October 2008
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Supply Noise Analyses Examples
Package simulation
Chip == current source
Chip grid IR drop analysis
Power Grid == Resistance
Are these the high levels of approximation (for design optimization) desirable??
October 2008
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On-Chip Analysis Challenge
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Atomic or Abstract?
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Polygonal Analyses
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Nanoscale IC’s today face
exploding computational
complexity (R, L, C, I, dI)
Energy & Efficiency
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October 2008
Analyze supply surface
ripples by ‘molecular’
interactions?
© 2008AnaSIM
Must know IC’s supply
ripples for optimization
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Meeting the Challenge
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Differential Power
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ECD: Continuum models
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Grid is uniform; treat as a
voltage-continuum along a
single surface USPTO PUB
Include R, L, C and solve
‘true-electromagnetically’
Abstract silicon, package
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October 2008
Voltage is a potential
difference; treat power
grid differentially
Partition hierarchically &
exploit symmetry
© 2008AnaSIM
Include distributed models
for silicon loads, CAP, pkg
and board components
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Abstraction & Physics-based Sims
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High levels of Abstraction
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Comprehensive Modeling
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All grid electromagnetic
properties, R, L, C used
Actual block load current
profiles used; di/dt, load
activity factors included
Physics based Simulation
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October 2008
Power GRID as SURFACE
DISTRIBUTED circuit load
currents & capacitance
SYMMETRY in physical as
well as electrical aspects
© 2008AnaSIM
Field solver employed for
Maxwell’s equations on
‘surfaces’ / NO ‘models’
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On-Die CAP for Noise Reduction
With Die Caps
Without Die Caps
Simple, lumped SPICE analyses indicate On-Die CAP helps in ΔVCC reduction
Area cost, Gate Oxide leakage are concerns
Reference: Narendra, ICCAD ‘03
October 2008
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SoC Power Integrity Simulation
R+L+C Dynamic Noise Simulation in
-fp
9 x 7mm
chip
Differential
noise
5nF /sq. cm
distributed
CAP
Explicit CAP
LENS
100mA peak
noise pulse
of 100ps
width
Pulse noise
source
Power grid
simulation
Do CAPACITORS (reactive devices) really absorb/expend noise energy?
Source: D. Bennett, ANASIM Corp.,
October 2008
-fp power integrity aware floor planner,
www.anasim.com
Use slide show © 2008AnaSIM Animation slide
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Resonant effects; More / Less CAP?
Single active circuit block in a 4x4mm IC
resonance
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-fp ‘what-if’ experiments showing effect of gate switching
time and on-chip de-cap on maximum voltage droop.
© 2008AnaSIM
October 2008
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CAP Connectivity & Noise
Analysis on a CLOCK chip
Corner CAPs connected to IO Ring
Corner CAPs connected to Core Grid
CAPACITOR blocks from IO ring corners connected into Core
power grid increased noise in the core grid
Source: ANASIM Corp.,
October 2008
-fp power integrity aware floor planner,
www.anasim.com
© 2008AnaSIM
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SoC Power Grid a Noise Conduit
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Low impedance grids
conduct and sum up
supply noise
Low energy loss in
global power grids 
more, sustained noise
Scaling and high perf.
 high local di/dt &
loop inductance leads
to greater local noise
Reference: Bennett, EEDesign 2003 article, www.anasim.com
October 2008
© 2008AnaSIM
Animation
slide
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Power Gating & Noise Flow
Power Gating transforms preferred pathways for noise flow in addition to transient
noise generation due to large switched capacitances…
Source: ANASIM Corp.,
October 2008
-fp power integrity aware floor planner,
www.anasim.com
© 2008AnaSIM
Animation
slide
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Example: System-level Chip Sim
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GUI or Netlist capture
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Experiment-1 results
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-fp simulation schematic illustration
(hyperlinked image)
October 2008
Chip NETLIST
Load current profiles are
pulse100gap100 and
pulse200gap200
SYMMETRY in physical as
well as electrical aspects
Chip grid ANIMATION &
Mirror
Notice substantial voltage
variation of top left corner
Cap 200pF added: results
© 2008AnaSIM
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Chip grid ANIMATION &
Mirror
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Chip Grid R, L + C Design
Maximum noise with grid wire width, 3nf cap
300
Noise at 10u wire width and varied on-chip cap
200
250
175
Noise (mv)
200
150
150
100
125
50
100
Noise (mv)
2
0
5
10
20
30
40
3
4
5
On-chip CAP (nf)
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Wire width (microns)
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With fixed on-chip capacitance value, increase in grid wire width
(reduction in resistance with minimal benefit in inductance)
reduces noise to a point
Increase in capacitance on-die has sub-linear benefit in noise
reduction; more CAP is not always good…
October 2008
© 2008AnaSIM
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How does it help design?
-fp bridges the PI gap
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Complements IR Drop
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Energy: Optimizes supply
traditional IC analysis with
true-electromagnetic sims
voltage domain levels
Optimizes power grids;
front-end CAP planning
Reduces cost: Routing,
Chip Area, Design Effort
October 2008
Minimizes costly design
iterations
© 2008AnaSIM
System-Level analysis
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Dynamic Energy Management
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Power  Performance,
Energy  Battery Life
Power & Energy
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Task completion at low
power with low frequency,
but same energy (PT)
 Must minimize voltage!
Circuits/Design in SoC’s
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Learning from CPUs’ VID bus and Adaptive
Voltage Positioning for Power Integrity
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Adaptive Voltage Scaling,
Dynamic Voltage scaling
PowerWise™ compliant
example in figure
Benefits in V-domains
Figure source: Mobile Handset Designline How To, 2007
October 2008
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External Voltage & Noise Control
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Distributed Local Voltage Regulation
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Multiplies bandwidth: smaller the regulator, faster it can be
Local placement ensures low latency, high loop bandwidth
Decentralized, simple, hardware energy management design
Issues: Component testing
Stacked Active Passives Integration (SAPI)
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Non-disruptive, practical and low-cost
References: Nair, US Patents 6084385, 6081105, 5955870, USPTO publication 20030081389, US Patent 7291896
October 2008
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Prescott-CPU ANR Inclusion
ANR Schematic & the PSC POR Model: Illustrations
30m
18n
R1
L1
5
V1
20m
6n
4m
385p
R3
L3
R4
L4
6m
R2
Trace
3.3n
L2
22u
C2
ANR Component
Q1
Reservoir CAP
Board
Package conn.
54p
vid
Vvr
0.42m
Rmb
Lmb
6m/n_osc
Rosc
504u
C1
18p
0.22m
0.26m
3.5p
Lsock Rsock
3.5m/n_mlcc
Rmlcc
Rpkg
6.5m/n_idc
Ridc
Lpkg
3.3n/n_osc
Losc
1.2n/n_mlcc
Lmlcc
60p/n_idc
Lidc
504u*n_osc
Cosc
20u*n_mlcc
Cmlcc
385p/n_2t
2.2u*n_idc
L2t
Cidc
Reference: Intel® Prescott CPU-PKG simulation model, ComLSI ANR
October 2008
© 2008AnaSIM
6.5m/n_2t
R2t
40ps/188n
Rdie
188n
Cdie
1
G1
V2
10u*n_2t
C2t
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Prescott Pre-ANR
Nom. VDD
October 2008
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Prescott Post-ANR
Nom. VDD
No spatial info,
V as f(x,y,t)
October 2008
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Advanced SiP Simulation
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Near load systems
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Active Noise Regulator*
Distributed Local (POL)
Voltage Regulators
Chip power grid noise
Spatial & Temporal
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Power supply variation
in x, y and t
Data can feed into
future Dynamic Timing
Analysis?
Simulation speed allows
‘what-if’ experiments
for optimization
Reference:
ANR attached to top left corner
* Nair & Bennett, ComLSI
Power Management Designline article http://www.powermanagementdesignline.com/howto/175800373
October 2008
Use slide show © 2008AnaSIM Animation slide
of grid
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Managing Leakage Power
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Classical techniques
Dual or Multi-VT processes
 High-K gate oxide
 SLEEP Transistors (gate-level)
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Threshold voltage modulation
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Adaptive Body Bias / Dynamic Body Bias
Supply voltage modulation
Most of these
complicate the
design/tool flow
substantially…
Adaptive Voltage Scaling / Dyn. Voltage Scaling
 Power Gating
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Scalable, fundamental solutions?
October 2008
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Addressing Scaling AND Power
Planar device Scaling
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VT, VDD reaching limits
Loss of channel control
Variations (VT, Leff…)
Leakage limiting gate
dielectric scaling
FinFET
Double Gate devices
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Lower leakage
Lower parasitics (C, R)
Lower fabrication cost
Lower delays  higher
performance!
Source: L. Mathew, SOI 2007
October 2008
© 2008AnaSIM
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Planar Contender from Intel®
High-K integrated, provides
low-leakage on-die CAP
30, 20 and 15nm transistors
claimed…
Reference: Marczyk & Chau, Intel®, 2005
October 2008
© 2008AnaSIM
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Double Gate Variants
FINFET
ITFET
MIGFET
Gate 1
Gate 2
Source: L. Mathew, SOI 2007
October 2008
© 2008AnaSIM
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Lower Total Cost of DG Devices
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Substantially reduced
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Improved
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Processing steps
Leakage
Parasitics/Performance
Record ION/IOFF
No area penalty /
greater area utilization
Novel circuits feasible
But challenges remain
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Process, Design
Source: L. Mathew, SOI 2007
October 2008
“Very promising for low power, low cost
Handheld
applications”
© 2008AnaSIM
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Summary
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Supply voltage minimization is key to IC energy
management
Accurate, true-electromagnetic, spatio-temporal
noise analysis essential
Innovative power delivery and integrity
management solutions are also needed
CMOS Scaling has some distance to go with
innovative devices
3-D (SiP, PoP, SAPI) integration will drive a more
feasible continuation of Moore’s Law
October 2008
© 2008AnaSIM
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Anasim Info
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Anasim bringing sea change into SoC
methodology with physics-based analyses and
high levels of abstraction
Benefits to chip resource usage, area, energy,
performance, and total design effort/cost
Fills the GAP in Total Power Integrity analyses
Non-disruptive, Win-Win-Win engagement
Links, tel. [email protected] +1 480-694-5984
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October 2008
Anasim White Papers pifp1.pdf, pifp2.pdf, pifp3.pdf
Product - -fp brochure
ComLSI, parent co.
© 2008AnaSIM
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Backup
October 2008
© 2008AnaSIM
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PI-FP Tool Environment
Simulation netlist
.TRAN 200e-12
.PLOT 20
.ACC 0.0060
.PRINTNODE ALL
Ggrid1 0.2 0.2 0.0005 0.0080 0.030
10e-9 10e-9
Igrid1 0.1 0.1 0.02 0.02 pulse.txt 1
Ttline1 1 2 0.01 10e-9 100e-12 0.3
Ngrid1 1 0.11 0.11
pulse.txt : Current Source
0
22E-12
40E-12
60E-12
80E-12
100E-12
120E-12
140E-12
160E-12
180E-12
200E-12
October 2008
© 2008AnaSIM
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0.030901699
0.058778525
0.080901699
0.095105652
0.1
0.095105652
0.080901699
0.058778525
0.030901699
0
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PI-FP Tool Environment contd.
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Multi-Grid design
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Planar or 3D
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© 2008AnaSIM
Include multiple
chips in stacked
or planar design
Code efficiency
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October 2008
L calculation
Each GRID on its
own core (CPU)
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Floorplanning / Optimization
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GRID wire width, spacing, pitch
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DECAP optimization
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Area savings
Block placement tweaks for PI
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Metal resource savings, routing / timing facilitation
Noise generation, propagation
Chip-Package co-simulation
Operating voltage (Energy) tuning
Resonance detection and avoidance…
October 2008
© 2008AnaSIM
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IO Ring impact on Core Noise
Analysis on a customer CLOCK chip
The voltage regulators, connecting between the IO Ring and the Core Grid
are seen to become significant noise injection nodes with the inclusion of
loads and the IO Ring. Pictures above are snapshots of dynamic plots.
October 2008
© 2008AnaSIM
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