Transcript Sisteme cu microprocesoare

Microprocessor-based Systems
Course 10 Design of Input/Output
interfaces (continuation)
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USB – Universal Serial Bus
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Goal:
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a communication standard for a wide range of
peripheral devices, connectable to a PC
 Mouse, keyboard, joy-stick – input devices
 Printer – output device
 Scanner, Digital camera, Webcam – multimedia
devices
 Memory-stick – storage devices
replaces traditional serial and parallel interfaces
Solution:
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multilayer protocol with master-slave functionality
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Performance features
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Very high speed
Wide bandwidth (12 Mbs)
PnP (Plag and Play) facilities
One interface handle many devices in the same time
Many communication channels on the same physical
support
Transmission modes adapted to different dataflow
types:
 sporadic data
 periodic data
 high volume of data
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Physical characteristics
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Transmission on standard cable:
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4 wires:
 2 for power supply: Vcc (red), GND (brown) => 5V,
500mA
 2 for data (blue and yellow ), twisted
Cable length:
 maximum 5 m
 extensible with HUBs until 30 m
Standard connectors:
 type “A” – for the computer (host or master)
 type “B” – for devices
Connectable during normal work (hot-swappable)
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Physical topology of the USB (network)
Host (computer)
Root Hub
Device
Device
Compound Device
Hub
Device
Hub
Device
Device
Star topology
Device
Device
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Device types:
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“Host” (master) – usually a computer
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the device that controls the communication on the USB
network
distributes network access rights to the other devices
moditors the USB network topology
“Device” – peripheral device connected to the computer
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offers a given “functionality” for the host (ex: mouse,
printer, scanner, etc.)
when it is connected the device gets a unique address from
the host
the format of data depends on the type of the device
information exchanged between the host and the device
may be:
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general information
information specific for a given type of devices
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Device types (cont.):
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“Hub” – amplifying and branching
device
“Compound Device” –
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contains a HUB and some devices
every device has its own address
(including the HUB)
“Composite Device” –
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contains a number of functionalities but
under a single address
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The USB protocol model
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the protocol is organized on three
hierarchical layers:
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USB bus interface layer – the physical layer
 handles the physical transmission of data (on
the cable)
USB device layer –
 assures the logical connection between the
host and the devices
 it is the operating system’s vision over the
USB interface
Function layer –
 assures the connection between the “client
software” in the host and the “function” in the
device
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The USB protocol model
Host
Device
Client software
Function
System software
Logical device
USB controller
Bus interface
Physical connection
Logical connection
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Logical topology (layer 2)
Host
Logical
Device
Logical
Device
Logical
Device
Logical
Device
• Direct connections between the host and the logical devices
• the physical connections (including HUBs) are ignored
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Application level topology
(layer 3)
Host
Client
software
Client
software
Client
software
Client
software
Dispozitiv
Function
Function
Function
Function
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Communication channels
Host
Client software
Buffers
Communication
flows
Device
Channels (Pipes)
Function
Endpoints
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Communication channels
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communication channel: a logical connection
between a device and a software that runs on the
host
a device may have a number of communication
channels
the host allocates a given bandwidth for every
channel according with:
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the type of the data transmission and
the available bandwidth
Every channel ends with an endpoint, used to:
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configure the data channel
address the channel
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Endpoints
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Endpoint: a part of a USB device:
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it is uniquely identified through a number
ends a communication channel
stores the parameters of a channel:
 bus access frequency
 required bandwidth
 endpoint’s number
 behavior in case of an error
 maximum length of accepted packages
 transfer type
 transfer direction
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Endpoints
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an USB device is a collection of endpoints
every device have two predefined endpoints, one
for input and one for output, both on address 0;
the other endpoints are not defined
the other endpoints are configured by the host,
when the device is connected
the endpoints are for input or for output
a communication channel is identified through:
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device address,
the endpoint number and
the dataflow direction
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Communication on the USB bus
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communication is made through frames of 1
millisecond (1000 cadre/s)
a frame contains a number of transactions
a given transfer may be performed through a
number of transactions
Transfer types on the USB bus:
 control transfer
 isochronous transfer, or periodic
 interrupt transfer or a-periodic
 bulk transfer or on blocks
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Control transfer
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initiated by the host, non-periodic
used for configuring and dialog with the device
a control transfer contains:
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a “setup” transaction – through which the device is
interrogated
zero ore more data transfers transactions
a status transaction – to find the state of the device
the control transfer is performed on a standard
channel present in every USB device
the standard channel is used for configuration and
for device interrogation
through this channel the host configures all the
other channels (including endpoints)
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Control transfer
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maximum dimension of the control packet may
be 8, 16, 32 or 64 bytes
the “setup” packet has a fixed dimension of de 8
bytes
the device descriptor specifies the maximum
accepted length for the data packets
the control transfers have lower priority than
isochronous or interrupt transfers
at most 10% of a frame is allocated for control
transfers, the rest is allocated for isochronous or
interrupt transfers
the control transfer used “handshake” in order to
guarantee the correctness of the transfer
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the erroneous packets are re-transmited
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Isochronous transfer (periodical)
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assures a guaranteed bandwidth for periodic
transfers
the format is not specified by the USB standard; it
depends on the type of the device, the content is
interpreted only at the client software level
the transfer is continuous, it ends only on an
explicit request
a reduced error detection mechanism, the
erroneous frames are not re-transmitted
the transfer through an endpoint is made in a single
direction; for bidirectional transfer two endpoints
must be defined
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Isochronous transfer (periodical)
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the maximum dimension of a packet is 1023
bytes
if more isochronous devices are used in the same
time the the packet dimension is divided
accordingly
the system allocates 90% of the bandwidth for
isochronous and interrupt transfers
every device will specify the required transfer
rate, which may be between 1 and 216 , (one
packet per several frames)
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Interrupt transfers
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used for sporadic, small data transfers
examples: mouse, keyboard, multiple channel
devices
maximum packet dimension: 64 bytes
a channel has a guaranteed bandwidth assured
through the allocation of a frame portion
during configuration, a minimum appearance
period is specified between 1-255 microseconds
during configuration the system verifies if the
required bandwidth necessary for a given
frequency can be assured
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Bulk transfer
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used for transferring blocks of data without time
restrictions
transfers are non-periodical
examples: printer, digital camera
the transfer will use the maximum available
bandwidth
the erroneous packets are re-transmitted
maximum packet dimensions: 8,16, 32, or 64 pt.
USB1.1 or 512 for USB 2.0
the bandwidth is not guaranteed
the priority is minimum
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Communication on USB
USBD
interface
HCD
interface
Client software
Data
USB Driver
Host Controller
Driver
Transfers
Transaction list
Transactions
Transaction
Hardware
interface
Transactions
Host Controller
Packets
USB
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Components involved in the communication
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Client software
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determines the type of the transfer for each
device
it does not handle communication channels
for communication uses the drivers offered by
the operating system
USB driver (USBD)
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handles the configuration and normal transfer
requests received from the client software
establish and configure communication
channels based on the received requests;
some requests may be rejected because of
bandwidth limitations
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Components involved in the communication
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Host controller’s driver (HCD)
 receives transfer requests and handles their
transmission
 puts the received data in the buffer
 checks the transmission limits (requests v.s
bandwidth)
 announce the end of the transmission
Transaction list
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contains the list of transactions in progress
Host controller
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transforms the waiting transactions in activities on
the bus
handles the frames and send and receive packets
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Parallel interface
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Transfer is made through a number of lines:
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Features:
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Data lines (ex: 8) – for data transmission
Control lines – for synchronization and dataflow
control
High speed
Small distances
Usually unidirectional transfers
Types of parallel transfers:
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a) without control signals
b) asynchronous protocol without confirmation
c) asynchronous protocol with confirmation (hand shaking)
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Transfer types
a) Without control signals
- only data lines are used
- useful for reading status lines or generating command signals
- cannot be used for sequential data transfer – there are no signals for
synchronization or flow control
- examples: testing digital sensors, control of actuators
b) asynchronous protocol without confirmation
- an extra control signal is used (besides data lines); it may be generated by
the emitter or by the receiver
- a sequence of data may be transmitted
- the transmission speed is controlled by the device generating the control
signal
- there is no feedback signal (confirmation) from the other partner; the speed
should be enough small to cover any possible delays; so the transmission is
slow
Data
RDY
Valid data
Data
Valid data
RQ
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Parallel transfer
c) Asynchronous protocol with confirmation (hand - shaking)
- two control signals are used: one from the emitter and one from the receiver
- transmission with “feed-back”
- it may be adapted to the variable speed of the emitter or receiver devices; the
result is a higher speed
- if the correlation between control signals is not good errors may occur
Data
Valid data
Data
RDY
RDY
ACK
ACK
(a)
(b)
Correct
Data
Valid data
Data 1
Error
Data 2
RDY
ACK
(c)
Error
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Parallel transfer
c) asynchronous protocol (hand - shaking), with interconditioning between control signals
- solves the correct transmission of data
- the control signals are inter-conditioned
Data
RDY
ACK
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Parallel transfer
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The I8255 circuit – controller for parallel transfers
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3 data ports of 8 bits (A, B and C)
Working modes:
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Inputs
Outputs
Bidirectional transfer
Port C divided in 2 in order to serve as control signals for
ports A and B A si B
Control
group A
D0-7
RD\
WR\
A0
A1
CS\
Data
Amp
Control
block
Port
A
PA0-7
½
C
PC4-7
½
C
PC0-3
Control
group B
Port
B
PB0-7
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Counter/Timer circuits
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Used for:
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Specialized controller:
I8253
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counting external events
generate different frequencies D0-7
by dividing a base clock
frequency
delaying signals (monoRD\
stable)
generate periodic interrupts WR\
3 counters of 16 bits
different working modes
CS\
A0,1
Data
amp
Counter
0
Out0
Clk0
Gate0
Counter
1
Out1
Clk1
Gate1
Counter
2
Out2
Clk2
Gate2
Ctrl
block
Cmd
reg
Use in a PC:
 to generate interrupts in
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order to measure the time
periodical memory refresh
cycles
to generate simple sounds
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Design of an Input/Output interface
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Steps
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Define the functional block scheme
select circuits for special interface functionalities (controllers)
allocate addresses for registers from the I/O space
establish the selection/decoding mode
design circuits for selection and control.
Functional blocks:
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selection/decoding block
Input/Output registers (ports)
Command device
Command register
Status register
Adaptation circuit for the peripheral device
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Design of an Input/Output interface
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Selection block:
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Role: Select the interface and the registers inside it
Selection mode:
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A9
A8\
A7
A6
A5\
A4
A3
5V
AEN
IOR\
IOW\
Total – all the address lines are considered (rarely
used)
Partial – a limited number of address lines are used
(most often used)
Linear – every address line is considered a
selection lie (used for small, dedicated systems)
A0
A1
A2
A
O0
B
O1
C
O2
DEC.
E\
E\
E
O7
74138
CSI\
CS0R\
CS0W\
CS1R\
CS1W\
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Design of an Input/Output interface
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Register block:
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Data registers/ports – for data transmission:
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Control register(s)
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generate control signals to the peripheral device or determine the
working mode of the interface
Status register(s):
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for Input
for Output
show the state of the interface or of the device
Data amplifier:
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assures the proper fan-out
Data bus
IOR\
CSI\
CS0W\
Dir 74LS245
CS\
CS0R\
Stb 74LS374
CS\
Output R
Output sign.
Bidirectional data
amplifier
Internal bus
CS1R\
G\ 74LS244
G\
Input R
Input sign.
G\ 74LS244
G\
Status R
Status sign.
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Circuits specialized for different
interfaces
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Parallel interface controller
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Serial interface controller
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SIO – serial I/O, or USART – universal serial
asynchronous receiver and transmitters: I8251
Counter/Timer controller:
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PIO – parallel I/O: I8255
CTC – counter/timer controller: I8253
Floppy disk controller: I8272
DMA controller: I8237
Interrupt controller: I8259A
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