Transcript Combinational Gates 4 - Electrical and Computer Engineering
Topics
Pseudo-nMOS gates.
DCVS gates .
Domino gates.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Pseudo-nMOS
Uses a p-type as a resistive pullup, n-type network for pulldowns.
a b Always on.
1 1 0 0 0 1 0 1 out 0 0 1 0 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Characteristics
Consumes static power.
Has much smaller pullup network than static gate.
Pulldown time is longer because pullup is fighting.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Output voltages
Logic 1 output is always at V DD .
Logic 0 output is above Vss.
V OL = 0.25 (V DD choice.
- V SS ) is one plausible Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Producing output voltages
For logic 0 output, pullup and pulldown form a voltage divider.
Must choose n, p transistor sizes to create effective resistances of the required ratio.
Effective resistance of pulldown network must be computed in worst case—series n types means larger transistors.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Transistor ratio calculation
In steady state logic 0 output: – pullup is in linear region,V ds V SS ) ; = V out - (V DD – pulldown is in saturation.
Pullup and pulldown have same current flowing through them.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Transistor ratio, cont’d.
Equate two currents with pull-down transistor in saturation and pull-up in linear region: – I dp = I dd . Using 0.5 mm parameters, 3.3V power supply: – W p /L p / W n /L n = 3.9.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
DCVS logic
DCVSL = differential cascode voltage logic.
Static logic—consumes no dynamic or static power.
Uses latch to compute output quickly.
Requires true/complement inputs, produces true/complement outputs.
The cascode (sometimes verbified to cascoding) is a universal technique for improving analog circuit performance, applicable to both vacuum tubes and transistors. The word was first used in an article by F.V. Hunt and R.W. Hickman in 1939, in a discussion for application in low-voltage stabilizers. They proposed a cascade of two triodes (first one with common cathode, the second one with common grid) as a replacement of a pentode.
http://en.wikipedia.org/wiki/Cascode Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
DCVS structure
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
DCVS operation
Exactly one of true/complement pulldown networks will complete a path to the power supply.
Pulldown network will lower output voltage, turning on other p-type, which also turns off p-type for node which is going down.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
DCVS example
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Precharged logic
Precharged logic uses stored charge to help evaluation.
Precharge node, selectively discharge it.
Take advantage of higher speed of n-types.
Requires multiple phases for evaluation.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Domino logic
Uses precharge clock to compute output in two phases: – precharge; – evaluate.
Is not a complete logic family—cannot invert.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Domino gate structure
Modern VLSI Design 3e: Chapter 3 Domino OR gate Copyright 1998, 2002 Prentice Hall PTR
Domino phases
Controlled by clock .
Precharge: p-type pullup precharges the storage node; inverter ensures that output goes low.
Evaluate: storage node may be pulled down, so output goes up.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Domino buffer
Output inverter is needed for two reasons: – make sure that outputs start low, go high so that domino output can be connected to another domino gate; – protects storage node from outside influence.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Domino operation
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Domino effect
Gate outputs fall in sequence: gate 1 gate 2 gate 3 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Monotonicity
Domino gates inputs must be monotonically increasing: glitch causes storage node to discharge.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Output buffer
Inverting buffer isolates storage node. Storage node and inverter have correlated values.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Using domino logic
Can rewrite logic expression using De Morgan’s Laws: – (a + b)’ = a’b’ – (ab)’ = a’ + b’ Add inverters to network inputs/outputs as required.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Domino and stored charge
Charge can be stored in source/drain connections between pulldowns.
Stored charge can be sufficient to affect precharge node.
Can be averted by precharging the internal pulldown network nodes along with the precharge node.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3
Homework Sets 3-4
Homework Set 3: Problems 2-13,2-19,2,pp. 106-108 Problems 3-1(c), 3.2(d), 3.7, 3.9, 3.12 pp. 179-181 Due, October 16, 2006. Homework Set 4: Problems 3-15, 3-16, 3.19(b), 3.20(b), p. 182.
Due, October 23, 2006.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 3