Transcript Chapter 6
Chapter 6 Exclusive-OR and Exclusive-NOR Gates William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. The Exclusive-OR Gate • HIGH output if one input or the other input is HIGH, but not both. • Logic Symbol - See Figure 6-3 • Truth Table - See Table 6-1 • Boolean equation – X = AB + AB • Comparator William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-3 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. The Exclusive-NOR Gate • • • • The complement of the exclusive-OR Logic Symbol - See Figure 6-4 Truth Table - See Table 6-2 Boolean equation – X = AB + A B • Comparator William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-4 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Parity Generator / Checker • Electrical noise in the transmission of binary information can cause errors • Parity can detect these types of errors • Parity systems – odd parity – even parity • Adds a bit to the binary information William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Parity Generator / Checker • See Figure 6-8 • Error indicator output • Even- and odd-parity generators – see Figure 6-9 • Integrated-Circuit Parity Generator/Checker – 74280 TTL IC – Function Table - see Figure 6-12 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-8 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-9 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-12 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. System Design Applications • See example 6-5, 6-6, and 6-7 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-13 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-14 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-15 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. CPLD Design Applications with VHDL • Used to simulate combinations of inputs and observe the resulting output to check for proper design operation. • See examples 6-8, 6-9, and 6-10 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. CPLD Design Applications with VHDL • Example 6-8, the 74280 parity geneator using the Quartus II Macrofunction – build a block design file – build a vector waveform file – provide a binary count on the 9 bit input so that several combinations of odd and even parity are generated William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-16 Figure 6-17 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. CPLD Design Applications with VHDL • Example 6-9, parallel binary comparator – reproduce the parallel binary comparator of example 6-6 – complete the circuit using bdf and VHDL entry methods – test operation William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-18 Figure 6-19 Figure 6-20 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. CPLD Design Applications with VHDL • Example 6-10, CPLD controlled inverter – reproduce the controlled inverter of example 6-7 – complete the circuit using bdf and VHDL entry methods – test operation William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Figure 6-21 Figure 6-22 Figure 6-23 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Summary • The exclusive-OR gate outputs a HIGH if one or the other inputs, but not both, is HIGH. • The exclusive-NOR gate outputs a HIGH if both inputs are HIGH or if both inputs are LOW. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Summary • A parity bit is commonly used for error detection during the transmission of digital signals. • Exclusive-OR and NOR gates are used in applications such as parity checking, binary comparison and controlled complementing circuits. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Summary • CPLDs can be used to implement circuits containing the exclusive gates William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.