Transcript Part 1 Module 4 Interrupts

Module 4 : Interrupt System C28x
32-Bit-Digital Signal Controller
TMS320F2812
Texas Instruments Incorporated
European Customer Training Center
University of Applied Sciences Zwickau (FH)
4-1
C28x Core Interrupt Lines
RS
NMI
INT1
INT2
INT3

INT4
C28x
CORE
INT5
INT6
INT7

2 non-maskable
interrupts (RS,
“selectable” NMI)
14 maskable interrupts
(INT1 – INT14)
INT8
INT9
INT10
INT11
INT12
INT13
INT14
4-2
C28x Reset Sources
C28x Core
Watchdog Timer
RS
RS pin active
To RS pin
4-3
Register Bits Initialized at Reset
Register bits defined by reset
PC
ACC
XAR0 - XAR7
DP
P
XT
SP
RPC
IFR
IER
DBGIER
0x3F FFC0
0x0000 0000
0x0000 0000
0x0000
0x0000 0000
0x0000 0000
0x0400
0x00 0000
0x0000
0x0000
0x0000
PC loaded with reset vector
Accumulator cleared
Auxiliary Registers
Data Page pointer points to page 0
P register cleared
XT register cleared
Stack Pointer to address 0400
Return Program Counter cleared
no pending interrupts
maskable interrupts disabled
debug interrupts disabled
4-4
Control Bits Initialized at Reset
Status Register 0 (ST0)
SXM = 0
OVM = 0
TC = 0
C=0
Z=0
Sign extension off
Overflow mode off
test/control flag
carry bit
zero flag
N=0
V=0
PM = 000
OVC = 00 0000
negative flag
overflow bit
set to left-shift-by-1
overflow counter
Status Register 1 (ST1)
INTM = 1
DBGM = 1
PAGE0 = 0
VMAP = 1
SPA = 0
LOOP = 0
EALLOW = 0
IDLESTAT = 0
AMODE = 0
OBJMODE = 0
M0M1MAP = 1
XF = 0
ARP = 0
Disable all maskable interrupts - global
Emulation access/events disabled
Stack addressing mode enabled/Direct addressing disabled
Interrupt vectors mapped to PM 0x3F FFC0 – 0x3F FFFF
stack pointer even address alignment status bit
Loop instruction status bit
emulation access enable bit
Idle instruction status bit
C27x/C28x addressing mode
C27x object mode
mapping mode bit
XF status bit
ARP points to AR0
4-5
Reset – Bootloader
XMPNMC=1
(microprocessor mode)
Reset
OBJMODE=0
ENPIE=0
AMODE=0
VMAP=1
Reset vector fetched
from XINTF zone 7
0x3F FFC0
M0M1MAP=1
XMPNMC=0
(microcomputer mode)
Reset vector fetched
from boot ROM
0x3F FFC0
Notes:
F2810 XMPNMC tied low internal to device
XMPNMC refers to input signal
Boot determined by
state of GPIO pins
Execution
Entry Point
FLASH
H0 SARAM
OTP
Bootloading
Routines
SPI
SCI-A
Parallel load
MP/MC is status bit in XINTFCNF2 register
XMPNMC only sampled at reset
4-6
Bootloader Options
GPIO pins
F4 F12 F3 F2
1
x
x
x
jump to FLASH address 0x3F 7FF6
*
0
0
1
0
jump to H0 SARAM address 0x3F 8000
*
0
0
0
1
jump to OTP address 0x3D 7800
*
0
1
x
x
bootload external EEPROM to on-chip memory via SPI port
0
0
1
1
bootload code to on-chip memory via SCI-A port
0
0
0
0
bootload code to on-chip memory via GPIO port B (parallel)
* Boot ROM software configures the device for C28x mode before jump
4-7
Reset Code Flow - Summary
0x3D 7800
OTP (2K)
0x3D 8000
FLASH (128K)
0x3F 7FF6
0x3F 8000
0x3F F000
H0 SARAM (8K)
Execution Entry
Boot ROM (4K)
Boot Code


RESET
0x3F FFC0
Point Determined
By GPIO Pins
0x3F FC00


BROM vector (32)
0x3F FC00
Bootloading
Routines
(SPI, SCI-A,
Parallel Load)
4-8
Interrupt Sources
Internal Sources
TINT2
TINT1
TINT0
EV and Non-EV
Peripherals
(EV, ADC, SPI,
SCI, McBSP, CAN)
External Sources
XINT1
XINT2
C28x CORE
RS
NMI
PIE
(Peripheral
Interrupt
Expansion)
INT1
INT2
INT3
•
•
•
INT12
INT13
INT14
PDPINTx
RS
XNMI_XINT13
4-9
Maskable Interrupt Processing
Conceptual Core Overview
Core
Interrupt
(IFR)
“Latch”
INT1
1
INT2
0
INT14
1
(IER)
(INTM)
“Switch” “Global Switch”
C28x
Core

A valid signal on a specific interrupt line causes the latch
to display a “1” in the appropriate bit

If the individual and global switches are turned “on” the
interrupt reaches the core
4 - 10
Interrupt Flag Register (IFR)
15
14
RTOSINT DLOGINT
13
12
11
10
9
8
INT14
INT13
INT12
INT11
INT10
INT9
7
6
5
4
3
2
1
0
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
Pending :
Absent :
IFR Bit = 1
IFR Bit = 0
/*** Manual setting/clearing IFR ***/
extern cregister volatile unsigned int IFR;
IFR |= 0x0008;
//set INT4 in IFR
IFR &= 0xFFF7;
//clear INT4 in IFR
Compiler generates atomic instructions (non-interruptible) for setting/clearing IFR
 If interrupt occurs when writing IFR, interrupt has priority
 IFR(bit) cleared when interrupt is acknowledged by CPU
 Register cleared on reset
4 - 11

Interrupt Enable Register (IER)
14
15
RTOSINT DLOGINT
13
12
11
10
9
8
INT14
INT13
INT12
INT11
INT10
INT9
7
6
5
4
3
2
1
0
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
Enable: Set
IER Bit = 1
Disable: Clear IER Bit = 0
/*** Interrupt Enable Register ***/
extern cregister volatile unsigned int IER;


IER |= 0x0008;
//enable INT4 in IER
IER &= 0xFFF7;
//disable INT4 in IER
Compiler generates atomic instructions (non-interruptible)
for setting/clearing IER
Register cleared on reset
4 - 12
Interrupt Global Mask Bit
Bit 0
INTM
ST1

INTM used to globally enable/disable interrupts:



Enable:INTM = 0
Disable:
INTM = 1 (reset value)
INTM modified from assembly code only:
/*** Global Interrupts ***/
asm(“ CLRC INTM”);
//enable global interrupts
asm(“ SETC INTM”);
//disable global interrupts
4 - 13
Peripheral Interrupt Expansion - PIE
Interrupt Group 1
1
INT1.2
0
•
•
•
INT1.8
INT1
1
28x Core Interrupt logic
INT8.x interrupt group
INT9.x interrupt group
INT1 – INT 12
INT10.x interrupt group
12 Interrupts
INT11.x interrupt group
•
•
•
INTM
96
INT3.x interrupt group
INT4.x interrupt group
INT5.x interrupt group
INT6.x interrupt group
INT7.x interrupt group
INT1.1
IER
INT1.x interrupt group
INT2.x interrupt group
PIEIFR1 PIEIER1
IFR
Peripheral Interrupts 12x8 = 96
PIE module for 96 Interrupts
28x
Core
INT12.x interrupt group
INT13 (TINT1 / XINT13)
INT14 (TINT2)
NMI
4 - 14
PIE Registers
PIEIFRx register
15 - 8
(x = 1 to 12)
7
reserved
6
5
4
3
2
1
0
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
PIEIERx register
15 - 8
(x = 1 to 12)
7
reserved
6
5
4
3
2
1
0
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
PIE Interrupt Acknowledge Register (PIEACK)
15 - 12
11
10
9
8
7
reserved
6
5
4
3
2
1
0
PIEACKx
PIECTRL register
15 - 1
PIEVECT
0
ENPIE
#include “DSP28_Device.h”
PieCtrlRegs.PIEIFR1.bit.INTx4 = 1;
//manually set IFR for XINT1 in PIE group 1
PieCtrlRegs.PIEIER3.bit.INTx5 = 1;
//enable CAPINT1 in PIE group 3
PieCtrlRegs.PIEACK.all = 0x0004;
//acknowledge the PIE group 3
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; //enable the PIE
4 - 15
Default Interrupt Vector Table at Reset
Prio
1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
4
2
3
-
Vector
Reset
Int 1
Int 2
Int 3
Int 4
Int 5
Int 6
Int 7
Int 8
Int 9
Int 10
Int 11
Int 12
Int 13
Int 14
DlogInt
RtosInt
EmuInt
NMI
Illegal
User 1-12
Offset
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
20
22
24
26
28-3E
Default Vector Table
Remapped when
ENPIE = 1
Memory
0
0x00 0D00
PIE Vectors
256 W
BROM Vectors
64 W
0x3F FFC0
0x3F FFFF
PIE vector generated by config Tool
Used to initialize PIE vectors
4 - 16
PIE Vector Mapping (ENPIE = 1)
Vector name PIE vector address
Not used
INT1
……
INT12
INT13
INT14
Datalog
……
USER11
INT1.1
……
0x00 0D00
0x00 0D02
……
0x00 0D18
0x00 0D1A
0x00 0D1C
0x00 0D1D
……
0x00 0D3E
0x00 0D40
……
PIE vector Description
Reset Vector Never Fetched Here
INT1 re-mapped below
…… re-mapped below
INT12 re-mapped below
XINT1 Interrupt Vector
Timer2 – RTOS Vector
Data logging vector
……
User defined TRAP
PIEINT1.1 interrupt vector
……
INT1.8
0x00 0D4E
PIEINT1.8 interrupt vector
……
……
……
INT12.1
0x00 0DF0
PIEINT12.1 interrupt vector
……
……
……
INT12.8
0x00 0DFE
PIEINT12.8 interrupt vector
 PIE vector space - 0x00 0D00 – 256 Word memory in Data space
 RESET and INT1-INT12 vector locations are Re-mapped
 CPU vectors are remapped to 0x00 0D00 in Data space
4 - 17
F2812/10 PIE Interrupt Assignment Table
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
WAKEINT
TINT0
ADCINT
XINT2
XINT1
INT2
T1OFINT
T1UFINT
T1CINT
T1PINT
INT3
CAPINT3
CAPINT2
CAPINT1
INT4
T3OFINT
T3UFINT
INT5
CAPINT6
INT1
INT6
INTx.3
INTx.2
INTx.1
PDPINTB
PDPINTA
CMP3INT
CMP2INT
CMP1INT
T2OFINT
T2UFINT
T2CINT
T2PINT
T3CINT
T3PINT
CMP6INT
CMP5INT
CMP4INT
CAPINT5
CAPINT4
T4OFINT
T4UFINT
T4CINT
T4PINT
MXINT
MRINT
SPITXINTA SPIRXINTA
INT7
INT8
INT9
ECAN1INT ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA
INT10
INT11
INT12
4 - 18
Device Vector Mapping - Summary
RESET
MPNMC = 0 (on-chip ROM memory)
Reset Vector
<0x3F FFCO> = Boot-ROM Code
Flash Entry Point <0x3F 7FF6 > = LB _c_int00
User Code Start
MPNMC = 1 (external memory XINTF)
Reset Vector <0x3F FFCO> = _c_int00
User Code Start < _c_int00>
< _c_int00 >
_c_int00:
. . .
CALL main()
main()
{ initialization();
. . .
}
Initialization ( )
{
EALLOW
Load PIE Vectors
Enable the PIEIER
Enable PIECTRL
Enable Core IER
Enable INTM
EDIS
}
PIE Vector Table
256 Word RAM
0x00 0D00 – 0DFF
4 - 19
Interrupt Response - Hardware Sequence
CPU Action
Description
Registers  stack
14 Register words auto saved
0  IFR (bit)
Clear corresponding IFR bit
0  IER (bit)
Clear corresponding IER bit
1  INTM/DBGM
Disable global ints/debug events
Vector  PC
Loads PC with int vector address
Clear other status bits
Clear LOOP, EALLOW, IDLESTAT
Note: some actions occur simultaneously, none are interruptible
T
AH
PH
AR1
DP
DBSTAT
PC(msw)
ST0
AL
PL
AR0
ST1
IER
PC(lsw)
4 - 20
Interrupt Latency
Latency
Internal
interrupt
occurs
here
ext.
interrupt
occurs
here
Assumes ISR in
internal RAM
cycles
4
2
Sync ext.
signal
(ext.
interrupt
only)
3
Recognition Get vector
delay (3) and (3 reg.
pairs
SP alignment
saved)
(1)
3
PF1/PF2/D1
of ISR
instruction
(3 reg. pairs
saved)
1
3
Save D2/R1/R2 of
return
ISR
address instruction
ISR
instruction
executed
on next
cycle
Above is for PIE enabled or disabled


Minimum latency (to when real work occurs in the ISR):

Internal interrupts: 14 cycles

External interrupts: 16 cycles
Maximum latency: Depends on wait states, ready, INTM, etc.
4 - 21
C28x CPU Timers
RESET
Timer Reload
16 - Bit divide down
TDDRH:TDDR
32 - Bit period
PRDH:PRD
16 - Bit prescaler
PSCH:PSC
32 - Bit counter
TIMH:TIM
SYSCLKOUT
TCR.4
BORROW
INT
4 - 22
C28x Timer Interrupt System
PIE unit
TINT0
INT1.7 interrupt
28x Core Interrupt logic
TINT2
INT14
INTM
INT13
IER
TINT1 / XINT13
IFR
INT1
28x
Core
4 - 23
C28x Timer Registers
Address
Register
Name
0x0000 0C00
TIMER0TIM
Timer 0, Counter Register Low
0x0000 0C01
TIMER0TIMH
Timer 0, Counter Register High
0x0000 0C02
TIMER0PRD
Timer 0, Period Register Low
0x0000 0C03
TIMER0PRDH
Timer 0, Period Register High
0x0000 0C04
TIMER0TCR
Timer 0, Control Register
0x0000 0C06
TIMER0TPR
Timer 0, Prescaler Register
0x0000 0C07
TIMER0TPRH
Timer 0, Prescaler Register High
0x0000 0C08
TIMER1TIM
Timer 1, Counter Register Low
0x0000 0C09
TIMER1TIMH
Timer 1, Counter Register High
0x0000 0C0A
TIMER1PRD
Timer 1, Period Register Low
0x0000 0C0B
TIMER1PRDH
Timer 1, Period Register High
0x0000 0C0C
TIMER1TCR
Timer 1, Control Register
0x0000 0C0D
TIMER1TPR
Timer 1, Prescaler Register
0x0000 0C0F
TIMER1TPRH
Timer 1, Prescaler Register High
0x0000 0C10 to 0C17 Timer 2 Registers ; same layout as above
4 - 24
C28x Timer Control Registers
TIMERxTCR
Timer Interrupt Flag
Write 1 clear bit
Emulator Interaction
1x = run free
Timer Interrupt Enable
Write 1 to enable INT
15
14
13
TIF
TIE
reserved
reserved
FREE
SOFT
7
6
5
4
3
2
reserved
reserved
TRB
TSS
reserved
reserved
Timer Reload Bit
1 = reload
12
11
10
9
reserved
1
reserved
8
reserved
0
reserved
Timer Stop Status
0 = start / 1 = stop
4 - 25