Transcript MIPS Pipeline and Branch Prediction Implementation

MIPS Pipeline and Branch
Prediction Implementation
Shuai Chang
Project Overview

ECE 369 Project Single Cycle Datapath
◦ Easy to implement
◦ Poor performance
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Performance Consideration
◦ Resource utilization
◦ Pipeline implementation
◦ Pipeline + Branch prediction
Original Design
Methodology
Implemented in Verilog HDL
 Simulation

◦ Xilinx ISE 13.2
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Hardware
◦ Xilinx Spartan 3E FPGA Devlopment Board
Methodology

Implementation
◦ Pipeline
◦ Branch prediction
Methodology

Inputs
◦ 2 files: Assembly Program and Data file
16 * 16 Window
32 * 32 Frame
X = 0, Y = 8,
SAD (Sum of Absolute Difference) = 0 is expected to be returned
Assembly Program Executed
Methodology

Outputs
◦ Returned X,Y
◦ SAD
◦ Execution Time = CycleCount * CriticalPathDelay
Results
Execute Time (ns)
Chart Title
20000000
15000000
10000000
5000000
0
1
Single Cycle
Pipelined
Pipeline + BP
Start Earlier?
Support more instructions
 Optimize logic
 Cache implementation

Questions?