Transcript Document

Nanoelectronic Memory Devices:
Space-Time-Energy Trade-offs
Ralph Cavin and Victor Zhirnov
Semiconductor Research Corporation
1
Main Points

Many candidates for beyond-CMOS nano-electronics have
been proposed for memory, but no clear successor has
been identified.


Methodology for system-level analysis
How is maximum performance related to device
physics?
SRC/NSF A*STAR Forum on 2020 Semiconductor Memory Strategies:
Processes, Devices, and Architectures, Singapore, October 20-21, 2009
http://grc.src.org/member/event/e003676/e003676_MeetingResults.asp
2
Space-Time-Energy Metrics

Essential parameters of the memory element are:






cell size/density,
retention time, access time/speed
operating voltage/energy.
None of known memory technologies, perform well
across all of these parameters
At the most basic level, for all memory elements, there is
interdependence between operational voltage, the speed
of operation and the retention time.
Cell dimensions are also part of the trade-off, hence the
Space-Time-Energy compromise
3
Space-Action Principle for Memory
Energy timeVolume min
E  t V  min
E  t  L  min
E  t  Nat  min
The Least Action principle is a fundamental principle
in Physics
E t  min (h)
Plank’s constant
h=6.62x10-34 Js
4
Three essential components of a
Memory Device:

1) ‘Storage node’


2) ‘Sensor’ which reads the state


e.g. transistor
3) ‘Selector’ which allows a memory cell in an array to be
addressed



physics of memory operation
transistor
diode
All three components impact scaling limits for all memory
devices
5
Three Major Memory State Variables

Electron Charge (‘moving electrons’)


Electron Spin (‘moving spins’)


e.g. DRAM, Flash
(STT-) MRAM
Massive particle(s) (‘moving atoms’)

e.g. ReRAM, PCM, Nanomechanical, etc.
Note: Electrical I/O always wanted
6
DRAM schematic
Problem 1: In Si devices Ebmax<Eg=1.1 eV
Barrier+Selector
p
Storage:
n
N carriers
n
Eb, eV Max. retention
0.6
0.65
0.75
1.1
1.6
1 ms
4 ms
84ms
~1 h
>10 years
Only volatile memory possible with FET barrier
7
Volatile electron-based memory: DRAM
Selector
Eb,C
dC
Sensor
Eb,tr
a
25fF
Storage Node
(a=10 nm, K=100)
Nel~105
Cint
88 fF
 0 ~
L
1cm
Vcap=10-15 cm3
Problem 2a: External sensing requires large Nel
Problem 2b: Large Nel requires large size of storage node (capacitor)
Problem 2c: Series resistance of the storage capacitor increases with scaling
8
Charge-based injection “easy” in
DRAM: Barrierless transport…
Write
K=100
a~10 nm
CV
tw 
 RC  RFET  Rcap  C
I
Dominates at
a<10 nm
(>25fF)
tw~0.1-1 ns
9
DRAM summary
Ta=1 s
Ta=10y
Ew~10-14 J
Ew~310-14 J
a=15 nm
a=30 nm
Volcap~5105 nm3
Volcap~106 nm3
VolFET=104 nm3
VolFET=105 nm3
EtV~10-9 J-ns-nm3
EtV~10-8 J-ns-nm3
DRAM inherent issues:
Selector
Sensor
-Low barrier height-Volatility
- Remote sensing – Large size of Storage node
10
Flash in the limits of scaling
Storage Node
Volstorage=2000 nm3
Nel~10
~10 nm
Sensor
Selector
~6nm
Nel~10
~20nm
VolFET~3a3 ~3000nm3
11
Voltage-Time Dilemma

For an arbitrary electron-charge based memory element,
there is interdependence between operational voltage,
the speed of operation and the retention time.

Specifically, the nonvolatile electron-based memory,
suffers from the “barrier” issue:


High barriers needed for long retention do not allow fast
charge injection
It is difficult (impossible?) to match their speed and voltages
to logic
12
Flash Summary
E~10-16 J
t~1 ms=1000 ns
Volstorage=2000 nm3
VolFET~3a3 ~3000nm3
EtV~10-9 J-ns-nm3
The minimum space-action metric is approximately
the same as for the DRAM
13
Conclusion on ultimate chargebased memories

All charge-based memories suffer from the “barrier”
issue:


High barriers needed for long retention do not allow fast
charge injection
It is difficult (impossible?) to match their speed and voltages
to logic

Voltage-Time Dilemma
Non-charge-based NVMs?
The Choice of Information Carrier
14
Spin torque transfer MRAM (Moving spins):
Energy Limit
 Eb 
 KV 
  f 0 exp
f tr  f 0 exp 

k
T
k
T
 B 
 B 
(f0~109-1010 c-1)
t store
 KV 
1

exp 

f0
k
T
 B 
tstore>10 y
the anisotropy
constant of a material
Eb = KV > ~1.4 eV
volume
D. Weller and A. Moser, “Thermal Effect Limits in Ultrahigh-Density Magnetic
Recording”, IEEE Trans. Magn. 36 (1999) 4423
15
FET selector is biggest component of STTMRAM in the limits of scaling
Eb = KV >1.4eV
K~0.1-1 J/cm3
(the anisotropy constant of a material)
volume
J-G. Zhu, Proc. IEEE 96 (2008) 1786
11 nm
Selecting FET
VolFET~3a3 ~3000nm3
Storage Node
V=1500 nm3
Nspin~105
16
STT-RAM summary
V=1500 nm3 (e.g. 11nm22 nm)
VolFET~3a3 ~3000nm3
Ew~Nspin  Eb~105  10-19~10-14 J
(Alternative estimate based on optimistic write current/write time projections:
Iw~107 A/cm2 and tw~1 ns
Ew~107 A/cm2  11nm2 1V 1 ns~10-14 J
EtV~10-11-10-10 J-ns-nm3
This looks a little better than the electron-based
we looked at earlier!
17
Scaled ReRAM (courtesy Dr. In YOO/Samsung)
18
Ultimate ReRAM: 1-atom gap

1
3
a ~ n Au  0.257 nm
ON/OFF~1.61
A
B
V=0.5 V
Eb=0.38 eV
dt=0.075 nm
dt<<a
Ultimate ReRAM: 2-atom gap

1
3
a ~ 2n Au  0.514 nm
ON/OFF~476
A
B
V=0.5 V
Eb=2.63 eV
dt=0.37 nm
dt<a
Ultimate Atomic Relay: 4-atom gap

1
3
a ~ 3n Au ~ 1nm
Eb (energy barrier for diffusion)
Energy
0.5-1 eV
 Eb 
 Eb 
m
  l0
ttr  t0 exp
exp
 ~ 2s
k BT
 k BT 
 k BT 
Ultimate Atomic Relay: 4-atom gap

1
3
a ~ 4n Au ~ 1nm
Eb (energy barrier for diffusion)
Energy
0.5-1 eV
3
3
 Eb 
 Eb 
m
  l0
ttr  t0 exp
exp
  10 y
k BT
 k BT 
 k BT 
(Eb=0.5 eV, n>5)
Ultimate ReRAM: A summary
a  1nm
V=1nm3
Nat~100
(64)
E~Nat*1eV~10-17J
tw~1 ns (can be shown)
EtV~10-17 J-ns-nm3
without FET
VolFET~3a3 ~3000nm3
EtV~10-14 J-ns-nm3
with FET
Summary
Ncarriers
Vstor,
nm3
Main constraints
due to sensor
SpaceAction, Biggest
Ew, J tw, ns J-ns-nm3 component
DRAM
105
105
10-14 1 ns ~10-8-10-9
Flash
10
103
10-16 103 ns
~10-9
Sensor
FET
103
10-14 1 ns
~10-10
Selector
FET
10-17
~10-14
Selector
FET
STT-RAM 105
ReRAM
100
1
without FET
1 ns
Storage Node
Constraints by sensor
not considered
VolFET~3000nm3
With FET
24
Summary





Memory cell design is a tradeoff between physical
variables needed to achieve long retention times, and short
write/read times.
A global metric, space-action, for all memory categories
provides insights into most promising extremely-scaled
memory devices based on fundamental physics
Scaling Limits of semiconductor component often dominate
overall scaling for the memory cell
Our preliminary study suggests a good potential for
ReRAM (some constraints are not considered)
Today’s memory technology meets Feynman’s challenge
of placing the 24 volumes of Encyclopedia Britannica
(~200 MB) on the head of a pin (~.025 cm^2).

Library of Congress (10 Terabytes) on 1 cm^2 by 2020?
25