Transcript The von Neumann Model – Chapter 4

1
The LC-3 – Chapter 5
COMP 2620
Dr. James Money
COMP 2620
Data Movement Instructions

Recall that there are three types of
instructions:
–
–
–
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Operate instructions
Data movement instructions
Control instructions
We consider the data movement instructions
today
Data Movement Instructions
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Remember these types of instructions move
data from registers to memory and back
For now, we will not consider the movement
of data from registers to input/output devices
We consider only to/from memory to general
purpose registers (GPRs)
Data Movement Instructions
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The process of move information from
memory to a register is called a load
The process of moving information from a
register to memory is called a store
In both cases, the source operand
completely overwrites the destination
operand
Data Movement Instructions

The LC-3 has the following movement
instructions:
–
–
–
–
–
–
–
LD – load PC relative
LDR – load base+offset
LDI – load indirect
LEA – load effective address
ST –store PC relative
STR – store base+offset
STI – store indirect
Data Movement Instructions

The format of the load and store instructions
is
15
14
Opcode

13
12
11
10
DR or SR
9
8
7
6
5
4
3
Address Generation Bits
Bits [11:9] is first operand, a register
–
–
–
DR = destination register
SR = source register
Depends on whether load or store
2
1
0
Data Movement Instructions
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Bits [8:0] contain the address generation bits
This encodes the information for the 16 bit
address of the second operand
There are four ways to interpret this
The opcode determines which way these bits
are interpreted
Base+Offset Mode
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The LDR (opcode = 0110) and
STR (opcode = 0111) use a base + offset
addressing mode
The name is derived from the fact the final
address is given by a base register and a 6
bit signed extended offset from the base
Base+Offset Mode
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The offset portion is a literal or immediate
operand using bits [5:0]
The base register is specified in bits [8:6]
The range of the offset is -32…31
Allows the memory location to be anywhere
in address space
LDR (Base+Offset)
STR (Base+Offset)
Base+Offset Mode
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Assume that R2 has the value 0x2345
Then, the instruction
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
0
0
0
1
0
1
0
0
1
1
1
0
1
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The is LDR R1, R2, 0x1D
We use that 0x2345+0x1D = 0x2362
Hence, R1=MEM[0x2362]
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Base+Offset Mode
Immediate Mode
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The last addressing mode is the immediate
addressing mode
It is used only by load effective address
(LEA, opcode = 1110)
LEA works by adding the signed extended
bits [8:0] to the incremented PC and storing
in the register in bits[11:9]
There is no memory access!
LEA (Immediate)
Immediate Mode

Consider the instruction:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
1
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This is LEA R5,-3
So, the result is R5=PC+-3
If the instruction is at 0x4018, R5 will have
the value 0x4016
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Immediate Mode
Example
Address
Instruction
Comments
x30F6
1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1
R1  PC – 3 = x30F4
x30F7
0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0
R2  R1 + 14 = x3102
x30F8
0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1
M[PC - 5]  R2
M[x30F4]  x3102
x30F9
0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0
R2  0
x30FA
0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1
R2  R2 + 5 = 5
x30FB
0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0
M[R1+14]  R2
M[x3102]  5
1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1
R3  M[M[x30F4]]
R3  M[x3102]
R3  5
x30FC
opcode