Transcript LAr Electronics

I discuss only the Barrel EM Lar - most advanced
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This is the FEC (Front End Crate at the
back of the EM calorimeter. This is
what is mostly discussed.
RADIATION: sufficient to necessitate
rad-hard technology, but relatively low
For one year at high luminosity (1041
cm-2) estimate:
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1-3 x 1012 n/yr (En > 100 keV) expressed
in terms of damage for 1 MeV neutrons
20 Gy/yr (Eg > 30 keV)
1010 ionising particles/yr
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In addition, optical links must survive
these doses (up to 1014 n and 1 Mrad g
over experimental life)
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This is within the cryostat and is
passive (except for Hadron End Cap
where GaAs preampli is included
It does however need rad control of
kaptons, glue etc.
Understood, under control, and not
further discussed
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This is connected to FEC by an optical link. It is
OUTSIDE the radiation zone (we are building the
RODs).
Final production prototypes of all (I think) units
exist and not time critical. A fully equipped backend crate will be used in the Front-End system test
foreseen end 2003 at BNL.
Not further discussed.
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FE Crate
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Full functionality was demonstrated by Module 0 electronics (~6k channels), used in testbeam measurements of CAL
modules for past several years
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Due to schedule constraints, was not required to be radiation tolerant
Three main blocks - calibration, analog shaping etc,
Results in a NIM paper that I will give to you, results summarised in part I for what concerns electronics
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First rad-tol prototypes of the various boards are now available
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A system test (1/2 crate) is last step before launching full production
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System test to be completed before end of 2003, with production to be launched beginning of 2004 (installation in ATLAS pit starts
11/2004)
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1.1 Radsoft Module 0
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Specifications and properties of FEB
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190 K channels, current preamplification with
Ipeak ~ 2.8 mA/GeV. Three types of preamplifier
are used, depending on the input impedance
(20pF - 3 nF). It is a 4-channel hybrid design.
Pulse shape triangular with rise time of a few
nsec, and decay time typically in range ~ 450
nsec depending on impedance - subsequent
shaping.
Shaper is a CR-RC circuit with t~13 ns.
After shaping the signal is sampled and stored
in SCA pipeline chip at 40 MHz.
Level 1 trigger rate is 75 kHz, resulting in need
for a 2.5 msec analog pipeline of the front end
chip (SCA).
This is all followed by ADC (5 MHz).
They aim for calibration circuitry with
uniformity and precision < 0.25%.
3 readout layers plus preshower layer - result is
typically 10-100 cells hit by a shower; for this
reason coherent noise must be kept low (<5% of
incoherent noise)
38 FEB’s were made
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Test bench performance of FEB’s for the 3
different preamp types
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Average noise C=0.3 nF and C = 1 nF
Preamp
High
gain
Medium
Gain
Low
gain
50 ohm, 1 mA
7 mV
1 mV
0.6 mV
25 ohm 5 mA
5.5 mV
0.9 mV
0.6 mV
25 ohm 10 mA
3.6 mV
0.8 mV
0.6 mV
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1.2 Radsoft Module 0
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Specifications and properties of CAL board
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Test bench performance of CAL boards
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10 CAL boards were made, each with 64
channels
Provide a signal like ionisation signal over full
dynamic range
Uniformity needed to 0.25%
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Noise and gain when connected to module 0
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Result:
- specs reached in rad soft prototype
-has to be repeated with the “production
rad hard electronics
NB: A similar full test has been made
with the HEC system
output shows a rise time of ~ 1 nsec and
exponential decay
On the top of the signal there is a small parasitic
charge which results in an integral nonlinearity
of ~0.1% for low and medium gain, a bit worse
for high gain\
Pulse uniformity measured to be 0.2% due
mainly to different cable lengths to input, after
correction rms is 0.11%
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Regular calibrations made when fully connected
to Module 0 in test beam. Non-linearity better
than 1% over full dynamic range, and stability
of gain over run period a few parts per mil.
Coherent noise on each FEB ~5% of incoherent
noise. The rms noise in high gain is ~ 10 MeV
(preshower), 11-13 MeV (front), 28-31 MeV
(middle) and 21-28 MeV (back).
For an typical electron cluster at n=0.26 the
total noise for high (medium) gain is 140 (260)
MeV, of which 95% (80%) is incoherent.
There were some problems with crosstalk, but
now studied and solved - a question also for
radhard case - worst effect is between electrodes
(max 4.1%)
Measured S/N for muons is 7.11±0.07
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2.0 RADHARD ELECTRONICS
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The following slides are based on the talk of
John Parsons at the last LHCC (July 2)
FEB boards now exist in rad-hard
technology, and also CAL, TRIG and CNTL
boards.
10 FEB boards have been made and 2
boards have been populated. The main
problem appears to be the Voltage
Regulator
A full system test of a FEC crate has yet to
be made. This will imply 20 FEB boards if I
understand. The system test is being
prepared in BNL and was foreseen this
summer. It is now hoped for end 2003 or
early 2004.
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2.1 Overview of Front End (FE) Component Issues
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Move to radhard FE electronics required development and qualification of a total of 15 custom
rad-tol ASICS (in various technologies):
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A limited number of COTs are needed (ADC, op-amps, GLink, line driver)
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10 in DMILL
4 in DSM (using rad-tol standard cell library) - deep sub-micron
1 in AMS BiCMOS
All custom ASICs are available, or are in production
Extensive radiation qualification procedures performed
All production COTs have been purchased and qualified, except for ADC for which common
ATLAS/CMS/LHCb order is to be signed very soon
LAr FE, and particularly the FEB boards, has extensive needs for voltage regulatoprs Vregs (both
+ and -)
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ST (Thompson) contracted by CERN to develop rad-tol Vregs for general LHC use
Positive Vregs (L4913) successfully developed, and production quantities avail.
Negative Vreg (L7913) design continues to have technical problems, and is significantly impacting our FE
electronics development - this is a major problem.
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2.2 LAr DMILL Chip Status - components for CAL, FEB etc boards
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LAr has 3 different DMILL wafer sets:
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- Temic DMILL process stops at end of 2003, and this has major impact on Lar schedule, as well as SCT etc - a real
problem
DMILL process is less radiation tolerant than originally foreseen - not a problem for Lar, but a big problem for SCT
etc
1. SCA (pipeline) production (200 wafers)
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robotic testing should be finished TODAY!
(> 85k SCA chips tested)
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there are enough good SCA chips
2. Analog wafers (12 wafers of BiMUX, opamp)
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wafers received in Jan. 2003
closure of ASAT France has led to lengthy (> 3 mo.) delays in packaging
tests on chips from first wafer have reasonable yield; remaining 11 sent for pkging
3. Digital wafers (27 wafers of SPAC, CALogic, CONFIG, SMUX, DAC)
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wafer processing underway, with delivery scheduled for August 2003
failure of ATMEL to deliver would have far-reaching consequences
• DSM replacements would need to be developed
• Significant re-design would be needed for ALL boards
DMILL situation is being monitored closely
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2.2 cont LAr DMILL Chip Status - components for CAL, FEB etc boards
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Rad levels of all tests …..
Type of radiation
TID
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SEE
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Expected
5 kRad
1.6 1012 n/cm2
7.7 1011 h/cm2
Tested
52 - 175 kRad
1.6 1013 n/cm2
7.7 1012 h/cm2
Rad test of DMILL Configuration Controller
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Tested to 10 x expected radiation - significant degradation, but meets specifications.
No latchup detected, 90% CL < 1 per 2.6 days. This is overestimate since only used in setup.
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2.3 LAr Deep Submicron (DSM) Chip Status - components for CAL, FEB etc boards
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3 LAr-specific DSM ASICs (SCAC, GainSel, CLKFO)
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MPW runs used to demonstrate design, rad. tolerance
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Engineering run (2 wafers) delivered April 22
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Tested to 10 x expected radiation - no degradation of performance and for full Lar barrel expect 1 latchup per
6.9 minutes (97-99% recoverable by redundancy, includes factror 10 safety)
Rad test of Commercial Triple Line Receiver
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Still in time for FEB production needs, but need to pay attention to schedule
Rad test of DSM SCA controller
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We have postponed (twice!) the irrad. tests, now re-scheduled for July 19/20
Once eng. run tests done, submit production order (45 wafers)
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Goals: produce final masks, determine yield, re-verify rad. tolerance
Due to pkg’ing delays, we still have not received the chips (expected mid-May)
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PRR passed in September 2002
Enough devices available for short-term needs
Tested to 10 x expected radiation - no degradation of performance and for full Lar barrel expect with safety
factor <130 latchups at 90% CL.
Rad test of DSM Gain Selector
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Tested to 10 x expected radiation - no degradation of performance and for full Lar barrel expect with safety
factor 1 latchup per 3.1 hours (most redundant)
Further radiation tests of the DSM components and custom components such as line receivers etc
are if I understand being made July/August 2003. No show stoppers expected.
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2.4 Radhard Voltage Regulator Status
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ST was contracted by CERN to develop rad-tol Vregs (both + and -)
Positive Vreg (L4913) successfully developed and now available in quantity
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Negative Vreg (L7913) has gone through several iterations, but continues to suffer from technical
problems
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have tried hard, but not succeeded, in finding a suitable alternate solution
To minimize delay, have proceeded with design of boards using L7913, and tested them as best as possible
(eg. with less-than-perfect L7913 samples, commercial Vregs, etc.) to be ready when L7913 becomes
available
On June 24, 10 JQ5 samples were received and immediately added to existing 2 FEB prototypes
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JQ3 (04/2002) – non-functional
JQ4 (11/2002) – functional, but tends to oscillate
JQ5 (06/2003) – more stable, but suffers from thermal instability for large loads
L7913 problems have significantly delayed FE system test, which was originally scheduled for
Summer 2002
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have been using these devices since early 2002
have received the full production quantity
Preliminary tests verify improved stability compared to JQ4.
It is possible the JQ5 thermal problem would not be serious in our application
Plan to proceed with FE system test using JQ5, and implement JQ6 when they arrive (October 2003)
L7913 continues to represent significant risk to FE electronics development
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2.5 Radiation Tolerant Front End Board
Front End Board (FEB) :
1524 boards @ 128 ch
in final system
Component rad tests being made (see slides), unclear to me whether a full board will be radiated
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2.6 Radiation Tolerant Calibration Board
Calibration :
116 boards @ 128 ch
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2.7 Radiation Tolerant Controller and Trigger Boards
Controller :
116 boards
Tower builder (TBB) :
120 boards @ 32 ch
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2.8 Radiation Tolerant LV Power Supply
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300 VDC brought to area of TileCal “fingers”
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FE crate requires 7 different DC voltages
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Technical solution with DC-DC convertors was developed through an
extended R&D and radiation qualification program
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Produce modules with specially chosen components
Provide redundancy due to SEU-burnout concerns
Contract awarded for production of 2 prototypes
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Significant delays incurred in finalizing services, requirements
Prototype delivery now scheduled for end August 2003
FE crate will have to start with other LVPS
Have only 60 days after prototype delivery to exercise option for full
production
Need to follow schedule very closely
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2.9 Front End Crate (FEC) Test
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Before proceeding to PRR and then production for the various FEC boards, plan a system test
with all boards together, filling the “basic unit” of ½ FEC
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FEC test setup will include:
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“dummy” calorimeter loads
cables (det  FT  baseplane)
FE crate, including:
• PWR/signal distribution
• water cooling
Prototype LV power supply
Controller, CALIB, TTB boards
From 1 FEB, to 14 FEBs
Prototype Monitor boards
DCS monitoring with ELMB
VME-based TTC + SPACMaster
Temporary VME-based readout for up to 16 FEBs
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2.10 FE Crate System Test in Preparation
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Setup prepared with 1 FEB, commercial PS
Plan to now produce remaining FEBs, populated with new
JQ5 Vreg samples
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Move to final power devices as available:
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Start FEC test in August
Identify and perform tests which can be done before final
Vreg, PS solutions are available
Prototype LVPS in September
JQ6 Vreg samples in October
Aim for FEC boards’ PRRs in late November
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FEC test schedule is very tight
Neg. Vreg and LVPS continue to present significant risks
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3.0 Summary
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Final prototypes of both FE and BE electronics boards are now available
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FE and BE system tests are scheduled to be completed by end of 2003
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Electronics production to start in early 2004
Installation in ATLAS pit to start by 11/2004
Main concerns continue to be:
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Negative Vreg
• Need to determine if either JQ6 or JQ5 version is suitable for production (10/03)
Rad-tol LVPS
• Need to test prototype and launch production (10/03)
DMILL
• Need successful delivery of LAr DMILL Digital Wafers (08/03)
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