Transcript FPCCD Vertex detector

FPCCD Vertex
detector
22 Dec. 2006
Y. Sugimoto
KEK
Vertex detector for ILC
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Performance goal：
Impact parameter resolution;
sIP = 5  10/(pb sin3/2q ) mm ( << ct of D, t )
This m.s. term is very challenging
• Very thin wafer, beam pipe, support
• Innermost layer as close to IP
as possible  High b.g. rate
 High pixel occupancy
Track density (/cm2/BX)
Vertex detector options
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If signals of one train (2820 bunches) are accumulated, too many
hits by beam b.g.  for 25 mm pixels, the pixel occupancy >10%
for B=3T and R=20mm
Solutions;
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Fast readout : Example; Column Parallel CCD @50MHz, 20 frames/train
 No time to wait for diffusion in epi-layer after particle incident
 Fully depleted CCD  No diffusion Poor resolution
 Still smaller pixel size is necessary to recover the resolution
 Possible effect by RF noise by beam
Analog registers in each pixel (~20/pixel), and readout between trains
 CMOS: Flexible Active Pixel Sensor (FAPS)
 CCD: In-situ Storage Image Sensor (ISIS)
 Fine and complicated structure  Large area OK?
Make pixel density x20Fine Pixel CCD (FPCCD)
Vertex detector options
Readout
between
trains
Si Pixel
Readout
during
train
Fine pixel
(x20 more
pixels)
FPCCD
Standard pixel
(x20 time slice
in 1 train)
FAPS
Standard pixel
(x20 time slice
in 1 train)
ISIS
MAPS
SOI
CPCCD
DEPFET
GLD Vertex detector
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FPCCD vertex detector as the baseline design of GLD
 Accumulate hit signals for one train (2840 BX) and read out
between trains (200ms)  Completely free from EMI
 Fine pixel of ~5mm (x20 more pixels than “standard” pixels) to
keep low pixel occupancy  Spatial resolution of ~1.5mm even
with digital readout
 Fully depleted epitaxial layer to minimize the number of hit pixels
due to charge spread by diffusion
 Two layers in proximity make a doublet (super layer) to minimize
the wrong-tracking probability due to multiple scattering
 Three doublets (6 CCD layers) make the detector
 Tracking capability with single layer using hit cluster shape can
help background rejection
 Multi-port readout with moderate (~20MHz) speed (Very fast
readout (>50MHz) not necessary)
 Simpler structure than FAPS or ISIS  Large area
 No heat source in the image area
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B.G. rejection by hit cluster shape
(tracking capability with single layer!)
Standard CCD
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High Pt
Signal
Low Pt
b.g.
Z
f
Fine Pixel CCD
Challenge of FPCCD
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Fully depleted
Lorentz angle
tanq=rHmB, rH: Hall coefficient~1,
m: mobility (m2/Vs), B: Magnetic
field (T)
 Stronger E-field in dep. layer
(>104V/cm = 1V/mm) gives
saturation of carrier velocity and
smaller m
 Epi layer of ~15mm would be OK
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Radiation tolerance
Small pixel （~5 mm)
Fast readout speed
（~20Mpix/s）
Multi-port readout
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H-Register in image area
Low noise:
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<50 e (total)  < 30 e (CCD)
Low power consumption
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Large area:10x65mm2（in）
/20x100mm2（out）
Thinning（<50 mm)
Full well capacity
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Metal layer
Low drive pulse voltage
Output circuit
>104 e is OK
Readout ASIC
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Necessary for proto-type
ladder
Lorentz angle
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tanq=rHmB~mB (m:m2/Vs, B:T), m=v/E
m~0.07 m2/Vs
m~0.1 m2/Vs
m~0.14 m2/Vs
R&D for FPCCD
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Study of fully depleted CCD
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Development of FPCCD
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3 rounds expected
Prototype ladder in 5 years
Collaboration with Hamamatsu
Minimization of material budget
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Charge spread
Lorentz angle
Radiation damage
Wafer thinning
FEA study of support structure
Development of readout ASIC
Supported by Gakujyutu Sousei
R&D Roadmap
2006
2007
2008
2009
2010
ILC Project (Detector)
DOD
DCR
LOI
Construction
Study of fully
Depleted CCD
2nd round
Design of small
Prototype of FPCCD
Sample test
FPCCD
fabrication
3rd round (prototype ladder)
Sample test
Sample test
Development of readout
ASIC for prototype CCD
FPCCD VTX
Wafer thinning and the support structure
Other 2nd priority R&Ds
DOD: Detector Outline Document
DCR: Detector Concept Report
LOI: Letter of Intent (?)
Short term plan
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Study of fully depleted CCD
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New CCDs will be delivered mid December
 Epi-layer: 30mm / 15mm
 Pixel size: 24mm
Study of charge spread and Lorentz angle
 Using green YAG LASER
 B-field up to 1T
Radiation tolerance
 Electron / neutron damage
 Dark current / charge transfer inefficiency
Study of support structure
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FEA study of Si-RVC-Si sandwich structure (RVC:
Reticulated Vitreous Carbon)
Study of charge spread
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Apparatus
CCD for test
(Back-illumination)
CCD for reference
(Front-illumination)
Charge spread
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Front illumination
Standard
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Back illumination
Deep2
Field simulation
NA=1.0, 1.5, 2.0, 2.5,
3.0, 3.5, 4.0 x1013/cm3
Summary
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We have started R&D of FPCCD for GLD vertex
detector
Study of fully depleted CCD is on going in FY2006,
and will be continued to FY2007
The 1st test sample of FPCCD is expected to be
made by Hamamatsu in FY2007
We wish to construct and test prototype ladders of
FPCCD by the end of Gakujyutu-Sousei project, but
the budget (for r.o. ASIC and support structure) is
not enough to complete that goal