Transcript Physical Properties of Logic Devices

Physical Properties of
Logic Devices
Technician Series
Created Mar 2015
©[email protected]
1
Timing Measurements
• Timing is a critical issue in digital electronics. Much of the
specification sheet for logic devices is devoted to timing
specifications.
• Different families of devices require different
measurements.
2
Waveform Measurement
Period (T)
Pulse Separation (Ps)
Pulse Width (Pw)
90%
Amplitude
50%
10%
Rise Time (tR)
Fall Time (tF)
Rise and fall times are typically
measured in nanoseconds (ηs)
3
Typical Waveform
• Due to the effects of inductance, capacitance, noise,
grounding, device properties and other factors, digital
signals tend to be electrically and timely less than perfect.
These effects are increased with frequency.
Over-shoot
Ringing
Pre-shoot
Droop
Typical Waveform
4
Timing problems cause glitches in Asynchronous counters
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
000
100
010
000
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Propagation Delay
6
Propagation Delay
• Propagation Delay is defined as the amount of time it
takes after an input signal is applied for the output to
change.
A
• Propagation Delay is caused by:
o Electron Speed in the medium
o Capacitance
B
• Propagation delay is usually measured in seconds
• Prop Delay varies by logic Family
7
Propagation Delay
• Propagation delay specifications state the direction of the
output pulse edge.
TpLH: Time Low to High change in output
TpHL: Time High to Low change in output
• Prop delay measurements are different for CMOS and
TTL devices.
8
Propagation Delay
CMOS measured at 50% mark
TTL measured at 1.5 Volt mark
9
Propagation Delay
• Typical propagation delays:
o TTL (7400)
• TpLH: 11s typical, 22s maximum
• TpHL: 7s typical, 15s maximum
o TTL (74S00)
• TpLH: 3s typical, 4.5s maximum
• TpHL: 3s typical, 5s maximum
o CMOS (4011B)
• TpLH: 125s typical, 250s maximum
• TpHL: 125s typical, 250s maximum
10
Example 1
• Determine the propagation delay for the following circuit,
assuming TpLH: 11s typical, 22s maximum and TpHL:
7s typical, 15s maximum.
Total Delay
• TpLH + TpHL + TpLH = 22s + 15s + 22s = 59s
•TpHL + TpLH + TpHL= 15s + 22s + 15s = 52s
•Total Propagation Delay is 59s
Worst case is used to predict the propagation delay
11
Input/Output Current
12
Gate Currents
Digital Logic devices are constructed from analog
components which include a variety of transistors,
resistors, diodes and other semiconductors.
TTL devices, based on
transistors, rely on current flow to
sense the input logic. Current
flow between the output of one
device and the input of the other
device is required to switch the
transistors on or off. The action
of the transistors is what
determines the output logic state.
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Source and Sink
• Every logic device will either source or sink current.
o When the gate output is in a high state, it sources current.
Sourcing = provides current
o When the gate output is in a low state, it sinks current.
Sinking = receives current
o Gate inputs can either sink or source current, depending on
the level of the output attached to it.
Current entering a gate is + (sink)
Current exiting a gate is - (source)
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Source and Sink
Output sinks current in a low state
Output sources current in a high state
15
Driving and Loading
• Driving gate: A gate that provides a logic level to other gates.
• Loading gate: A gate that receives a logic level from other gates.
Driving Gate
Loading Gates
16
Input and Output Current
• IIL: Input Low Current. Current when input is in a low state.
• IIH: Input High Current. Current when input is in a high
state.
• IOL: Output Low Current. Current when output is in a low
state.
• IOH: Output High Current. Current when output is in a high
state.
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Input and Output Current
18
Typical Current Values
• 7400:
o
o
o
o
IIL:-1.6mA
IIH: 40A
IOL:16mA
IOH: -0.4mA
• 74LS00:
o
o
o
o
IIL:-0.4mA
IIH: 20A
IOL:8mA
IOH: -0.4mA
19
Power
20
Some Definitions
• Quiescent: output logic that is not changing (also known as static)
• Dynamic: output logic that changes (also known as switching)
•
•
•
•
VCC: TTL Supply Voltage
ICC: TTL Supply Current
ICCH: TTL Supply Current with all outputs high.
ICCL: TTL Supply Current with all outputs low.
•
•
•
•
•
VDD: CMOS Supply Voltage
VSS: CMOS Ground
IDD: CMOS Supply Current (static/quiescent)
IT: CMOS Supply Current (static and dynamic)
CPD: CMOS Internal Capacitance
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Power (TTL)
• Power = Voltage  Current = VCC  ICC
Vcc & Icc
22
Device Input Current (TTL)
• With all the outputs = logic high
• Input current = ICCH specification
ICCH
1
1
1
Make the outputs logic
high by applying the
appropriate input logic
1
23
Device Input Current (TTL)
• With all the outputs = logic low
• Input current = ICCL specification
ICCL
0
0
0
Make the outputs logic
low by applying the
appropriate input logic
0
24
TTL Power Calculation
• Power = Voltage  Current = VCC  ICC
• If all gates are high:
o Pd = VCC  ICCH
o ICC = ICCH
• If all gates are low:
o Pd = VCC  ICCL
o ICC = ICCL
Assume Vcc = 5V, unless otherwise specified
25
Device input current (TTL)
ICC
DC=25%
0
In this example, ¼ of the gates are at 25% duty cycle, ¾
are logic low.
Pd= Vcc(¼@(0.25ICCH+0.75  ICCL) + (¾ @ ICCL))
Pd= Vcc((0.25(0.25ICCH+0.75ICCL) + (0.75ICCL))
0
0
Remember: A duty cycle of 25% means that the output is high for 25% of
the time (using ICCH), and low for 75% of the time (using ICCL).
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CMOS Power
• CMOS uses very little power in the static state (in the order
of W).
• As switching increases (more dynamic), so does power
consumption. This is primarily due to capacitance.
• Power requirements also increase with ambient temperature.
As temperature increases, so does power consumption.
• Static power consumption for a B-Series gate  500W
maximum
• Other families of CMOS have lower power consumption.
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CMOS Power Calculation
• Most CMOS specification sheets provide the
mathematical equation for calculating power
consumption.
• Care must be taken when utilizing the specification
sheet.
o Current is specified per gate or per IC package. Read carefully.
o Formulas may vary (example: 4011B compared to the 4027B)
o IDD is different from IT
• Generally:
IT (pac kage
)  (I / kH z)  f   IDD
IT (gate)  (I / kH z)  f   IDD / N
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Input/Output Voltages
29
Voltage and Logic Values
• Digital logic is represented as a voltage value.
• We are accustomed to assuming the following:
o Logic high = 5V
o Logic Low = 0V
• In reality:
o Applied voltage values, and the resultant logic highs and lows, vary
by device family.
• Some logic operates on 3.3 Volts, others on 12 Volts and yet
other applications operate on a +12/-12 Volt logic.
o many digital logic devices produce logic values that are not ideal.
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Voltage Issues
• When designing systems, we must ensure that the logic
voltage output of a (driving) gate will be interpreted
properly by the receiving (loading) gate.
Vcc 1
Vcc 2
31
Output Voltage Specifications
• VOH: Voltage Output High.
o Minimum voltage produced for
a high state.
VOH
Minimum
• VOL: Voltage Output Low.
o Maximum voltage produced
for a low state.
VOL
Maximum
Output
Voltage
Some TTL logic high outputs can be as little as 2.4
volts (on a 5 Volt system).
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Input Voltage Specifications
• VIH: Voltage Input High.
o Minimum voltage required for
a high state.
VIH
Minimum
• VIL: Voltage Input Low.
o Maximum voltage required for
a low state.
VIL
Maximum
Input
Voltage
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Voltage Output/Input
VCC
VOH
VIH
Minimum
Minimum
Undefined
Undefined
Maximum
VOL
VIL
Maximum
Output
Input
Ground
Gate inputs that receive voltage levels within the undefined zone
are unable to reliably determine the logic level.
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Voltage Characteristics
• IC’s must have minimum and maximum criteria for output
levels.
o For output, the high must have a minimum acceptable voltage level
o For output, the low must have a maximum acceptable voltage level
• IC’s must have minimum and maximum criteria for input
levels
o For input, the high must have a minimum acceptable voltage level
o For input, the low must have a maximum acceptable voltage level
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Noise Margin
36
Noise
• Noise: Unwanted electrical signal.
• Noise Margin: The ability to tolerate noise.
o Noise margin defines the difference between the worst-case
voltage output and input levels.
• CMOS devices have larger input logic level ranges,
making them less susceptible to noise.
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Voltage Output/Input
VCC
VOH
VIH
Minimum
Minimum
Undefined
Undefined
Maximum
VOL
VIL
Maximum
Output
Input
Ground
Noise Margin
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Noise
Anticipated Signal
HIGH
HIGH
Undefined
Undefined
Undefined
LOW
LOW
Output
Input
Actual Signal
with Noise
39
Improved Noise Margin
Anticipated Signal
HIGH
HIGH
Undefined
Undefined
LOW
LOW
Output
Input
Actual Signal
with Noise
40
Noise Margin Calculation
• Noise Margin is the difference between the worst-case
output voltages to the worst-case input levels.
VnH  VOH  VIH
VnL  VIL  VOL
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Noise Margin Example
• 4011B:
o
o
o
o
4.95 V
Minimum
VOH: 4.95 V
VOL: 0.05 V
VIH: 3.5 V
VIL: 1.5 V
Minimum
Maximum
0.05 V
1.5 V
Maximum
Output
VnH  VOH  VIH  4.95  3.5  1.45VnH
VnL  VIL  VOL  1.5  0.05  1.45VnL
3.5 V
Input
Noise Margin
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Noise Margin Example
• 7400:
o
o
o
o
VOH: 2.4 V
VOL: 0.4 V
VIH: 2 V
VIL: 0.8 V
2V
2.4 V
Minimum
Minimum
Maximum
0.4 V
VnH  VOH  VIH  2.4  2  0.4VnH
VnL  VIL  VOL  0.8  0.4  0.4VnL
Maximum
Output
0.8 V
Input
Noise Margin
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Interfacing CMOS and TTL
• Although CMOS and TTL device families have
different electrical characteristics, they can be
interfaced.
• Fanout and Noise Margin are characteristics that
must be accounted for in the design process.
• Propagation delay and power are other important
considerations.
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CMOS TO TTL
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CMOS
TTL
Noise Margin Calculation
CMOS 4011B:
o VOH: 4.95 V
o VOL: 0.05 V
TTL 74LS04
o VIH: 2V
o VIL: 0.8V
46
CMOS
TTL
Noise Margin Calculation
CMOS 4011B:
o VOH: 4.95 V
o VOL: 0.05 V
TTL 74LS04
o VIH: 2V
o VIL: 0.8V
VnH  VOH  VIH  4.95V  2V  2.95V
VnL  VIL  VOL  0.8V  0.05V  0.75V
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CMOS
TTL
Noise Margin Calculation
• With a VnH of +2.95V and a VnL of +0.75V, there are
no noise margin problems with this circuit design.
Minimum=4.95V
Minimum=2.0V
CMOS
TTL
Maximum=0.8V
Maximum=0.05V
Output
Input
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CMOS
TTL
Noise Margin Calculation
CMOS 4011B:
– IOH: -0.51mA
– IOL: 0.51mA
TTL 74LS04
– IIH: 20A
– IIL: -0.4mA
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CMOS
TTL
Noise Margin Calculation
O utput_ Low
O utput_ H igh
IOL  0.5 1mA
IOH  0.5 1mA
IIL  0.4mA
IIH  2 0A
IOL  IIL  0.5 1mA  0.4mA  1.2 7 5 IOH  IIH  0.5 1mA  2 0A  2 5.5
Worst-case = 1 gate input
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CMOS
TTL
Noise Margin Calculation
• Most CMOS devices can drive at least 1 TTL input
from either the voltage or current perspective.
Read the introduction in the specification
sheet for the CMOS device.
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TTL to CMOS
52
TTL
CMOS
Noise Margin Calculation
• TTL 74LS04
CMOS 4011B:
o VOH: 2.7V
o VOL: 0.5V
o VIH: 3.5 V
o VIL: 1.5 V
53
TTL
CMOS
Noise Margin Calculation
• TTL 74LS04
o VOH: 2.7V
o VOL: 0.5V
CMOS 4011B:
o VIH: 3.5 V
o VIL: 1.5 V
Voltage
Problem
VnH  VOH  VIH  2.7V  3.5V  0.8V
VnL  VIL  VOL  1.5V  0.5V  1.0V
54
TTL
CMOS
Noise Margin Calculation
There is a problem with the noise margin.
Minimum=3.5V
Minimum=2.7V
CMOS
TTL
Maximum=1.5V
Maximum=0.5V
Output
Input
55
TTL
CMOS
Noise Margin Calculation
• The VOH of the TTL gate is too low for the
CMOS gate to reliable determine a high input.
VnH  VOH  VIH  2.7V  3.5V  0.8V
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In-Class Discussion
• Interface Circuits:
o
o
o
o
o
o
Improve Current
Improve Noise Margin
Shift Voltages
Switch Loads
Operate with positive and negative logic
Dealing with LED Loads (review)
57
Conclusion
When mixing logic families, it is important to:
• review the specification sheets
• make the necessary calculations to ensure the
devices will function properly
• utilize interfacing devices if needed
58
Review Questions
• What is the difference between:
o
o
o
o
o
Loading and Sinking inputs
Driving and Sourcing inputs
Fanout and Noise Margin
ICC and ICCH
IDD and IT
59
END
© [email protected]
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