Transcript TMS320C55x DSP Design Workshop

DSP C5000
Chapter 6
TMS320C54x and C55x
Interrupt Management
Copyright © 2003 Texas Instruments. All rights reserved.
Managing Interrupts
C54x DSP
C55x DSP
QUIT
ESIEE, Slide 2
Copyright © 2003 Texas Instruments. All rights reserved.
Objectives

Identify interrupt sources

Identify the requirements for interrupt recognition

Describe the sequence of events during an interrupt
ESIEE, Slide 3
Copyright © 2003 Texas Instruments. All rights reserved.
Interrupt Timeline
I
N
I
T
1.
2.
3.
4.
C
P
U
5. Valid signal
6. Flag bit set
7. Int enabled?
I
S
R
8. Context save/ISR/context restore
9. Return to main program
ESIEE, Slide 4
Select interrupt sources
Create interrupt vector table
Enable individual interrupts
Enable global Interrupts
branch to ISR
Copyright © 2003 Texas Instruments. All rights reserved.
1. C5409 Interrupt Locations
Interrupt
RS
NMI
SINT17-30
INT0
INT1
INT2
TINT
BRINT0
BXINT0
BRINT2/DMAC0
BXINT2/DMAC1
INT3
HINT
BRINT1/DMAC2
BXINT1/DMAC3
DMAC4
DMAC5
Reserved
ESIEE, Slide 5
Offset (Hex)
00
04
08-3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78-7F
Priority
1
2
-3
4
5
6
7
8
9
10
11
12
13
14
15
16
--
Description
Reset
Nonmaskable Int
S/W Int 17-30
Ext’l Int #0
Ext’l Int #1
Ext’l Int #2
Timer Int
McBSP #0 Rcv Int
McBSP #0 Xmt Int
McBSP #2 Rcv Int/DMA
McBSP #2 Xmt Int/DMA
Ext’l Int #3
HPI Int
McBSP #1 Rcv Int/DMA
McBSP #1 Xmt Int/DMA
DMA Ch4 Int
DMA Ch5 Int
Reserved
Ch0 Int
Ch1 Int
Ch2 Int
Ch3 Int
Copyright © 2003 Texas Instruments. All rights reserved.
2. Creating VECTORS.ASM
RSV:
NMV:
.sect
BD
STM
“vectors”
Reset
#STK+LEN,SP
Put NMI
routine here …
...
IV1:
BD
PSHM
PSHM
ISR1
ST0
ST1
IV2:
BD
PSHM
PSHM
...
ISR2
ST0
ST1
ESIEE, Slide 6

Each vector is always
4 words long

Unused vectors:
Debug
IVn: BD
NOP
NOP
IVn
Production
IVn: BD
Uh_oh
NOP
NOP
Copyright © 2003 Texas Instruments. All rights reserved.
3. Enable Individual Interrupts
IMR (Interrupt Mask Register)
Rsvd
15
Rsvd
14
DMAC5
DMAC4
13
12
BXINT2 BRINT2 BXINT0 BRINT0
7
6
5
;disable:
;enable:
set:
modify:
ESIEE, Slide 7
4
BXINT1 BRINT1
HINT
INT3
11
10
9
8
TINT
INT2
INT1
INT0
3
2
1
0
0
1
STM #102h,IMR
ORM #40h,*(IMR)
ANDM #0FFBFh,*(IMR)
Copyright © 2003 Texas Instruments. All rights reserved.
4. Enable Global Interrupts (INTM)
ST1
INTM
15
12
10
enable:
RSBX INTM ;0
disable:
SSBX INTM ;1
 Does
0
not affect bits in IMR
 INTM=1
ESIEE, Slide 8
11
(disabled) at reset
Copyright © 2003 Texas Instruments. All rights reserved.
5. C5409 External Interrupt Pins/Signals
'C5409
INT0-3

4 maskable external
interrupts (INT0-3)

2 non-maskable
external interrupts
(NMI, RESET)

Interrupt acknowledge
(IACK)
NMI
RESET
IACK
Recommendation

Do not use NMI as a high-priority interrupt. Because the state of INTM
is not saved, returning to main code from an NMI could result in undesired
behavior.

Use NMI only when you do not intend to return to main code.
ESIEE, Slide 9
Copyright © 2003 Texas Instruments. All rights reserved.
5. C5409 Internal Interrupt Signals
'C5409
SW Reset
McBSPs
DMAs
SW INTs
HPI
Timer
ESIEE, Slide 10

Software RESET does not set
IPTR to 1FFh

McBSP channel 0 rcv & xmit

McBSP channels 1 & 2 rcv &
xmit shared with DMA channels
0-3

DMA channels 4 & 5

Host Port Interface

Timer
Copyright © 2003 Texas Instruments. All rights reserved.
Recognizing Interrupts
What events/conditions are required to recognize an interrupt?
(IFR)
(IMR)
(INTM)
"Latch" "Switch" "Big Switch"
INTx
2
3
1
’C54x
0
core
INTy
ESIEE, Slide 11
1

External interrupts must meet the timing shown

IFRbit must be set to: “1”

IMRbit must be enabled: “1”

INTM must be enabled: “0”
Copyright © 2003 Texas Instruments. All rights reserved.
Pending Interrupts
IFR (Interrupt Flag Register)
Rsvd
15
Rsvd
14
DMAC5
DMAC4
13
12
BXINT1 BRINT1
BXINT2 BRINT2 BXINT0 BRINT0
7
6
5
4
HINT
INT3
11
10
9
8
TINT
INT2
INT1
INT0
3
2
1
0
;interrupt pending: “1”
clear_INT0: ST #1,*(IFR)
ESIEE, Slide 12

Writing a “0” to any IFRbit does nothing

IFR zeroed on reset
Copyright © 2003 Texas Instruments. All rights reserved.
Post Interrupt Hardware Sequence
CPU Action
Description
1  INTM
Disable global interrupts
PC  - - *(SP)
Push PC onto predecremented stack
Vector(n)  PC
Load PC with int. vector “n” address
0  IACK pin
IACK signal goes low
0  IFR (n)
Clear corresponding interrupt flag bit
Minimum interrupt latency is 7 cycles from a synchronous interrupt event to the
fetch of the first ISR instruction. Add 2-3 cycles for an external interrupt.
ESIEE, Slide 13
Copyright © 2003 Texas Instruments. All rights reserved.
Context Save & Restore Instructions
Instruction
Description
PSHM
mmr
SP - 1  SP
Push MMR onto Stack
POPM
mmr
SP + 1  SP
Pop from Stack to MMR
Smem
SP - 1  SP
Push Data memory value onto Stack
Smem
SP + 1  SP
Pop top of Stack to Data memory
PSHD
POPD
FRAME K
SP + K  SP
Modify Stack Pointer
Restore registers in the opposite order in which they were saved
ESIEE, Slide 14
Copyright © 2003 Texas Instruments. All rights reserved.
Return Instructions
Instruction
Actions
RET[D]
*(SP) ++ 
PC
RET
RETD
5
3
RETE[D]
*(SP) ++ 
0 
PC
INTM -
RETE
RETED
5
3


PC
INTM -
RETF
RETFD
3
1
RTN
RETF[D]
0
*(SP) ++
Using RETF[D]:
ESIEE, Slide 15
Cycles

3-cycle ISR

No calls, no nesting
RINT0: RETFD
MVKD
NOP
DRR0,*AR7+%
Copyright © 2003 Texas Instruments. All rights reserved.
What’s Missing?
ESIEE, Slide 16

Nesting interrupts

Relocating the vector table

Software interrupts

Reset

Interrupts in a Far Environment

Timer
Copyright © 2003 Texas Instruments. All rights reserved.
Nested Interrupts
PSHM
IMR
Save IMR
STM
#5,IMR
Enable only Interrupts 0 and 2
RSBX
INTM
Enable Interrupts
; Nestable ISR . . .
SSBX
INTM
Disable Interrupts INTM - =1
POPM
IMR
Restore IMR value
RETE
ESIEE, Slide 17
Copyright © 2003 Texas Instruments. All rights reserved.
Relocating the Vector Table
1
SMUL
SST
1 1 1 1 1 1 1 1
AVIS
DROM
CLKOFF
PMST
MP/MCOVLY
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPTR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Interrupt
Vector
Address
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
Reset
Interrupt
Vector
Number
ESIEE, Slide 18
4-word
align
0 0 0 0 0
Copyright © 2003 Texas Instruments. All rights reserved.
Software Interrupts
INTR
TRAP
RESET
k
k

k: interrupt number (see documentation)

INTR = TRAP + disables INTM

RESET instruction performs all tasks that a
hardware reset does except:
- it does not set IPTR to all 1’s
- it does not reset the internal peripherals
ESIEE, Slide 19
Copyright © 2003 Texas Instruments. All rights reserved.
Hardware Reset
ESIEE, Slide 20
Math
Memory
0  OVA/OVB/OVM
0  OVLY,DROM
0  C16,ASM,FRCT
?  MP/MC
1  SXM,C
1FFh  IPTR
Pins
Misc
1  XF
0  BRAF
0  CLKOFF
0  DP, CPL
0  AVIS, HM
1  INTM

A[x]: driven to FF80h, D[16]: high impedance

An internal reset is sent to the peripherals.

Seven CLKOUT cycles after RS- is released the
processor will fetch from 0FF80h
Copyright © 2003 Texas Instruments. All rights reserved.
Interrupts in a Far Environment

Only the “local” (16-bit PC) address is automatically saved on the stack

However, when using extended memory (XPC is nonzero), how can you
safely return to the interrupted code?
1 Vector table located on the same 64K page as interrupted code
2 Set OVLY=1, copy vector table and ISRs to lower 32K, use:
IntVec_n:
PSHM
B
ST0
ISR_n
ISR_n: ...
RETE
3 Set OVLY=1, copy vector table to lower 32K, use FAR instructions:
IntVec_n:
ESIEE, Slide 21
PSHM
PSHM
FB
XPC
ST0
ISR_n
ISR_n: ...
FRETE
Copyright © 2003 Texas Instruments. All rights reserved.
Timer Operation

20-bit s/w programmable down-counting timer
Timer
TCR/1
15
0
9
TIM/1
Timer Control
TCR
15
- start/stop/reload
6
PSC
0
PRD/1
3
When TIM/PSC = 0:


0

Generate CPU int (TINT)
TOUT goes active
PRD/TDDR TIM/PSC
TDDR
TINT0/1
TOUT0/1
20-bit Timer



TIM: Timer
PRD: Period
PSC: Prescaler
TINT rate =
ESIEE, Slide 22
TDDR:
Timer Divide Down Ratio
‘5402 includes 2 timers
1
CLKOUT x ( TDDR+1 ) x ( PRD+1 )
Copyright © 2003 Texas Instruments. All rights reserved.
Timer Registers
15
0
15
0
TIM/1
PRD/1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR/1 Reserved
S F
o r
f e
t e
PSC
T T
R S
B S
TDDR
TSS
0: run, 1: stop
TRB
1: PRD  TIM
TDDR  PSC

At reset, the timer is running.

Startup Procedure
1. TCRTSS = 1 (stop timer), TCRTRB = 1, TDDR = desired value
2. Initialize PRD to desired value
3. TCRTSS = 0 (start timer)
ESIEE, Slide 23
Copyright © 2003 Texas Instruments. All rights reserved.
Answers
1. What are the interrupt sources?
Reset, NMI, Timers, Serial Ports, DMA, External, Software
2. How do you poll for interrupts?
Test the appropriate bit in IFR, then branch to ISR if TC set
3. What must you set up to respond to an interrupt?
INTM-, IMR, SP and a vector
4. What conditions affect interrupt latency?
Higher priority interrupts, IMRbit=0, processor is in
hold mode, INTM = 1, memory speed, Not READY, ...
ESIEE, Slide 25
Copyright © 2003 Texas Instruments. All rights reserved.
LAB - Managing Interrupts
1. Convert your previous assembly routine to an ISR
2. Set up timer registers to generate an interrupt
3. Set up interrupt registers to respond to timer interrupt
4. Modify VECTORS.ASM to add a new vector
5. Modify current assembly code to output 1 new result
each time the ISR is invoked
6. Graph results to verify
Time: 60 minutes
ESIEE, Slide 26
Copyright © 2003 Texas Instruments. All rights reserved.
LAB.ASM – Solution 1 of 3
.mmregs
.def start,fir
STKLEN
.set
a
y
BOS
.usect "coeffs",16,1
.usect "result",200
.usect "STK",STKLEN
table
x
start:
ESIEE, Slide 27
100
.sect "init"
.int 7FCh,7FDh,7FEh,7FFh
.int 800h,801h,802h,803h
.int 803h,802h,801h,800h
.int 7FFH,7FEH,7FDH,7FCH
.sect "indata"
.copy "in6.dat"
.sect "code"
STM
#BOS+STKLEN,SP
STM
#0,SWWSR
LD
#0,DP
ORM
#1,@PMST
SSBX
FRCT
RSBX
OVM
SSBX
SXM
;setup stack pointer
;set ext'l wait state to zero
;set SST bit (saturate on store)
;set FRCT bit (fractional mode)
;clr OVM bit (overflow mode)
;set SXM bit (sign extension)
Copyright © 2003 Texas Instruments. All rights reserved.
LAB.ASM - Solution 2 of 3
main:
CALL
fir_setup
;setup pointers for fir ISR
STM
STM
STM
#30h,TCR
#30h,PRD
#20h,TCR
;auto reload TIM/PSC, stop timer
;init period to 30 cycles
;start timer
STM
STM
RSBX
#0FFFFh,IFR
#8,IMR
INTM
;clear any pending interrupts
;enable TINT bit in IMR
;turn ON global interrupts
ADD
ADD
B
#1,A
#1,B
main
.asg
.asg
.asg
AR2,TOP
AR3,BOTTOM
AR4,RESULTS
fir_setup:
STM
STM
STM
STM
RET
ESIEE, Slide 28
#x+15,BOTTOM
#x,TOP
#y,RESULTS
#-8,AR0
;setup ARs for MAC
Copyright © 2003 Texas Instruments. All rights reserved.
LAB.ASM - Solution 3 of 3
fir:
done:
ESIEE, Slide 29
PSHM
PSHM
PSHM
PSHM
PSHM
PSHM
AL
AH
AG
BL
BH
BG
;context save
ADD
RPTZ
FIRS
MAR
MAR
STH
*TOP+,*BOTTOM-,A
B,#7
*TOP+,*BOTTOM-,#table
*TOP+0
*+BOTTOM(#10)
B,*RESULTS+
;prime FIRS w/add of two data values
;execute FIRS 8 times (16 products)
POPM
POPM
POPM
POPM
POPM
POPM
POPM
POPM
BG
BH
BL
AG
AH
AL
ST1
ST0
;context restore
RETE
;store result
;pushed in vectors.asm
;return from interrupt
Copyright © 2003 Texas Instruments. All rights reserved.
VECTORS.ASM - Solution
.def
rsv
.ref
start,fir
.mmregs
.sect
"vectors"
rsv:
B
RETE
RETE
start
RETE
RETE
RETE
RETE
;Non-maskable Interrupt Vector
. . .
RETE
RETE
RETE
RETE
BD
PSHM
PSHM
ESIEE, Slide 30
;Software Interrupt 18 Vector
fir
ST0
ST1
;Timer Interrupt Vector
Copyright © 2003 Texas Instruments. All rights reserved.
C54 Interrupt Complete
End of C54x Interrupt management study
Return
ESIEE, Slide 31
Copyright © 2003 Texas Instruments. All rights reserved.
Objectives

Analyze the Interrupt Timeline for the C55x
the order of events related to interrupts

Describe other interrupt issues (reset,
relocating vectors, priority, etc)

LAB - Convert your assembly routine
into an ISR
ESIEE, Slide 32
Copyright © 2003 Texas Instruments. All rights reserved.
Interrupt Timeline
I
N
I
T
1.
2.
3.
4.
C
P
U
5. Valid signal
6. Flag bit set
7. Int enabled?
I
S
R
8. Context save/ISR/context restore
9. Return to main program
ESIEE, Slide 33
Select interrupt sources
Create interrupt vector table
Enable individual interrupts
Enable Global Interrupts
branch to ISR
Copyright © 2003 Texas Instruments. All rights reserved.
C5510 Interrupt Sources
Interrupt
RESET
NMI
INT0/1/2
INT3/4/5
TINT0
TINT1
R/XINT0
R/XINT1
R/XINT2
DMAC0
DMAC1
DMAC2
DMAC3
DMAC4
DMAC5
DSPINT
ESIEE, Slide 34
Offset (hex/byte)
0
8
10/80/18
58/98/B8
20
B0
28/88
30/38
60/68
90
48
A0
A8
70
78
50
40,D8-FF
Description
Reset
Non-maskable
Ext’l Ints 0,1,2
Ext’l Ints 3,4,5
Timer #0 Int
Timer #1 Int
McBSP#0 Rcv/Xmt
McBSP#1 Rcv/Xmt
McBSP#2 Rcv/Xmt
DMA Ch0 Int
DMA Ch1 Int
DMA Ch2 Int
DMA Ch3 Int
DMA Ch4 Int
DMA Ch5 Int
Host Int (HPI)
Software Ints
Copyright © 2003 Texas Instruments. All rights reserved.
Creating VECTORS.ASM
;vectors.asm
rsv:

int0:
0:
.sect “vectors”

1-3: 24-bit address of ISR
.ivec start,USE_RETA

4-7: 1-4byte executed instruction
Reset vector can specify stack mode:
.ivec NMI_ISR

C54X_STK: 32-bit stk (default)
INSTR

USE_RETA: 16-bit stk w/RETA

NO_RETA: 16-bit stk w/o RETA
.ivec INT0_ISR

ESIEE, Slide 35
stk_mode or don’t care


nmi:
Vector “packet” is 8 bytes long:
.ivec directive does the following:
 fills remaining bytes with NOPs if not used

aligns each vector to an 8-byte boundary

places the target address in bytes 1-3
Copyright © 2003 Texas Instruments. All rights reserved.
Enable Individual Interrupts (IER0/1)
IER0 (Interrupt Enable Register 0)
DMAC5 DMAC4 XINT2 RINT2 INT3 DSPINT DMAC1 Rsvd
15
14
13
12
11
XINT1 RINT1 RINT0 TINT0 INT2
7
6
5
4
3
10
9
8
INT0
Rsvd
Rsvd
2
1
0
IER1
INT5 TINT1 DMAC3 DMAC2 INT4 DMAC0 XINT0 INT1
7
ESIEE, Slide 36
6
5
4
3
2
enable:
OR
disable:
AND #k16,mmap(@IER0)
1
0
#k16,mmap(@IER0)
Copyright © 2003 Texas Instruments. All rights reserved.
Enable Global Interrupts (INTM)
INTM
ST1_55
15
12
11
0
enable:
BCLR
INTM
disable:
BSET
INTM

Does not affect bits in IER0/1

INTM=1 (disabled) at reset
Creating a macro:
INTS_OFF .macro
ESIEE, Slide 37
10
Using a macro:
. . .
BSET INTM
INTS_OFF
.endm
. . .
Copyright © 2003 Texas Instruments. All rights reserved.
C5510 External Interrupt Pins/Signals
'C5510
INT0-5

6 maskable external
interrupts (INT0-5)

2 non-maskable
external interrupts
(NMI, RESET)

Interrupt acknowledge
(IACK)
NMI
RESET
IACK
ESIEE, Slide 38
Copyright © 2003 Texas Instruments. All rights reserved.
Recognizing Interrupts
What events/conditions are required to recognize an interrupt?
(IFRx)
(IERx)
(INTM)
"Latch" "Switch" "Big Switch"
INTx
1
2
1
’C55x
0
core
INTy
ESIEE, Slide 39
1

External interrupts must meet the timing shown

IFRxbit must be set to a “1”

IERxbit must be enabled (“1”)

INTM must be enabled (“0”)
Copyright © 2003 Texas Instruments. All rights reserved.
Interrupt Flag Register (IFR0/1)
IFR0
DMAC5 DMAC4 XINT2 RINT2 INT3 DSPINT DMAC1 Rsvd
15
14
13
12
11
XINT1 RINT1 RINT0 TINT0 INT2
7
6
5
4
3
10
9
8
INT0
Rsvd
Rsvd
2
1
0
IFR1
INT5 TINT1 DMAC3 DMAC2 INT4 DMAC0 XINT0 INT1
7
6
5
4
3
2
1
0
 Write a 1 to clear a bit
clear:
MOV
#mask,mmap(@IFR0)
Writing a “0” to any IFR bit does nothing
ESIEE, Slide 40
Copyright © 2003 Texas Instruments. All rights reserved.
Post Interrupt Hardware Sequence
CPU Action
Description
PC  Stacks#
Copy return address (PC) to stacks
Registers  Stacks
see next slide...
1  INTM
Disable global interrupts
ISR address  PC
Load PC with ISR address
0  IACK pin
IACK signal goes low
0  IFR0/1 (n)
Clear corresponding interrupt flag bit

Min latency is 6 cycles from a synchronous interrupt event to the
fetch of the first ISR instruction. + 2-3c for an external interrupt.
 # depends
ESIEE, Slide 41
on stack configuration (32-bit or 16-bit stack)
Copyright © 2003 Texas Instruments. All rights reserved.
View of Stacks Before ISR
SSP
CFCT : RETA [23:16]
SP
RETA [15:0]
DBSTAT
ST1
ST0 [15:9] : 0
ST2
used
used
System Stack
User Stack

DBSTAT: used for emulation purposes

RETA:
return address
Only these items are automatically saved by the CPU
ESIEE, Slide 42
Copyright © 2003 Texas Instruments. All rights reserved.
Context Save & Restore Instructions
Save
Restore
PSH src
POP dst
PSH src1,src2
POP dst1,dst2
PSH src,Smem
POP dst,Smem
PSH ACx
POP ACx
PSH Smem
POP Smem
PSH dbl(Lmem)
POP dbl(Lmem)



ESIEE, Slide 43
User is responsible for context save/restore
Values must be popped in the reverse order that they are pushed
STx is not considered “src” or “dst”. Use PSH mmap(@STx).
Copyright © 2003 Texas Instruments. All rights reserved.
Return From ISR
RETI
RETI instruction does the following:

Pops all CPU-pushed values from the stacks (see step 7)

Returns program control to the interrupted task

INTM is restored to it’s previous state because ST1_55
is saved/restored automatically
ESIEE, Slide 44
Copyright © 2003 Texas Instruments. All rights reserved.
Objectives

Analyze the Interrupt Timeline - the order
of events related to interrupts

Describe other interrupt issues (reset,
relocating vectors, priority, etc)

LAB13 - Convert your assembly routine
into an ISR
ESIEE, Slide 45
Copyright © 2003 Texas Instruments. All rights reserved.
What Happens When Reset Occurs ?

All current operations are aborted, pipeline is flushed, registers are
initialized, reset vector is fetched

List of key registers and their initialized values:
Interrupts
IVPH/D = FFFFh
IFRn
= 0h
INTM
= 1

Address Registers
XARn = 0h
XDP = 0h
XSP = 0h
Status Bits
C54CM = 1
M40 = 0
FRCT = 0
CPL = 0
SXMD = 1
ARMS = 0
SATD = 0
Recommendation: do not rely on initialized values - always initialize
the necessary registers to the desired value during the reset ISR
Refer to the CPU Reference Guide for a complete list of reset values
ESIEE, Slide 46
Copyright © 2003 Texas Instruments. All rights reserved.
Relocating the Vector Table

Can be relocated to any 256-byte program page

Vector table is split into two types of vectors: DSP, host
DSP (IVPD)
Host (IVPH)
IV0…1V15
IV16…1V23
IV24…IV31

Allows host vectors to be placed in the DSP’s shared memory
area to support host access and ISRs

Relocating the 24-bit vector address using the IVPD/IVPH Registers:
23
8
IVPD/IVPH

7
3
Int #
2
0
0 0 0
On reset, IVPD/IVPH = FFFFh
ESIEE, Slide 47
Copyright © 2003 Texas Instruments. All rights reserved.
Interrupt “Priority”
There are three types of interrupt “priority”...
Hardware Priority

Selects which interrupt is serviced only when multiple interrupts occur
at the same time or if INTM is set to 0 when more than one IFRx bit is set

Based upon fixed priority as shown in the datasheet (e.g. Reset is highest,
NMI is next, etc)
Software Priority

User can select which interrupts are interruptible by “higher priority”
interrupts by modifying the IERx register. For example, when servicing
INT0 (higher hardware priority than INT3), user can modify IER to allow
INT3 to interrupt INT0.
BIOS SWI Priority

Within BIOS, hardware interrupts have a fixed priority (same as
“hardware priority” above. However, SWIs (software interrupts) are
managed easily within the BIOS Configuration Manager (more later)
ESIEE, Slide 48
Copyright © 2003 Texas Instruments. All rights reserved.
Review
1. What are the interrupt sources?
Reset, NMI, Timers, Serial Ports,
Host (HPI), DMA, External, Software
2. How do you poll for interrupts?
Test the appropriate bit in IFRx, then goto ISR if TCx set
3. What must you set up to respond to an interrupt?
INTM, IERx, SP/SSP and a vector
4. What conditions affect interrupt latency?
Higher priority interrupts, IERbit=0, processor is in
hold mode, INTM = 1, memory speed, ...
ESIEE, Slide 50
Copyright © 2003 Texas Instruments. All rights reserved.
LAB - Managing Interrupts
1. Convert your previous assembly routine to an ISR
2. Set up the appropriate registers to respond to interrupts
3. Modify VECTORS.ASM to add a new vector
4. Modify current assembly code to output 2 new results
each time the ISR is invoked
5. Graph results to verify
Time: 60 minutes
ESIEE, Slide 51
Copyright © 2003 Texas Instruments. All rights reserved.
LAB.ASM – Solution 1 of 3
x0
.sect "indata"
.copy in7.dat
.def
start,fir
.cpl_off
.arms_off
.c54cm_off
stklen
a0
y0
BOS
BOSS
table
.set
.usect
.usect
.usect
.usect
100
"coeffs",16,1,1
"results",200,1,1
"STK", stklen,1,1
"SSTK",stklen,1,1
.sect "init"
.int 7FCh, 7FDh,
.int 800h, 801h,
.int 803h, 802h,
.int 7FFh, 7FEh,
7FEh,
802h,
801h,
7FDh,
7FFh
803h
800h
7FCh
.sect "code"
start:
main:
ESIEE, Slide 52
AMOV #BOS+stklen, XSP
MOV #BOSS+stklen,SSP
;set up Stack and
;System Stack Pointers
MOV
MOV
MOV
#8,mmap(@IER0)
#0xFFFF,mmap(@IFR0)
#0xFFFF,mmap(@IFR1)
;Turn on INT2 and clear ints
CALL
CALL
BCLR
ADD
ADD
B
copy
firsetup
INTM
#1,AC0
#1,AC1
main
;copy coeffs
;setup for fir math
;Enable Global Interrupts
;main loop
Copyright © 2003 Texas Instruments. All rights reserved.
LAB.ASM – Solution 2 of 3
copy:
AMOV
AMOV
RPT
MOV
RET
#table,XAR2
#a0,XAR3
#7
dbl(*AR2+),dbl(*AR3+)
;load pointers
FRCT
M40
SXMD
C54CM
;turn on multiplier shift
;turn on 40 bit math
;turn on sign extension
;go to C55 native mode
AMOV
AMOV
AMOV
AMOV
MOV
#x0,XAR2
#x0+1,XAR3
#y0,XAR4
#a0,XCDP
#13,T0
;initialize pointers
;for data,
;results
;and coeffiecients
;set up TO for ptr wrap
MOV
MOV
MOV
#a0,BSAC
#16,BKC
#0, CDP
;buffer start address
;buffer size
;zero lower bits of XCDP
firsetup:
BSET
BSET
BSET
BCLR
BSET CDPLC
;move from table to a
;turn on circ addressing
RET
ESIEE, Slide 53
Copyright © 2003 Texas Instruments. All rights reserved.
LAB.ASM – Solution 3 of 3
fir:
PSH
PSH
AC0
AC1
;save AC0 and 1
MPY *AR2+,*CDP+,AC0
:: MPY *AR3+,*CDP+,AC1
;AC0 gets 1st product
;AC1 gets 2nd product
|| RPT #13
MAC *AR2+,*CDP+,AC0
::
MAC *AR3+,*CDP+,AC1
;RPT in parallel with MPYs
;form 14 results
MAC
:: MAC
*(AR2-T0),*CDP+,AC0
*(AR3-T0),*CDP+,AC1
;form last result and wrap pointers
MOV
pair(hi(AC0)),dbl(*AR4+)
;store AC0 & AC1 results
POP
POP
AC1
AC0
;restore AC0 and 1
RETI
ESIEE, Slide 54
Copyright © 2003 Texas Instruments. All rights reserved.
INT.ASM - Solution
.def RSV
.ref start
.ref fir
.sect "vectors"
RSV:
.ivec
start,USE_RETA
NMI:
.ivec
NMI
INT0:
.ivec
INT0
INT2:
.ivec
fir
TINT0:
.ivec
TINT0
RINT0:
.ivec
RINT0
RINT1:
.ivec
RINT1
;fir ISR
; etc etc etc
ESIEE, Slide 55
Copyright © 2003 Texas Instruments. All rights reserved.
INT2.DAT
to simulate interrupts, the following line must be
; used by CCS to know WHEN to fire the interrupt.
; RESET, NMI and SINT2-23 (INT0- to DSPINT) are supported.
;
100 (+60) rpt EOS
;
;
;
;
first interrupt occurs at the 100th cycle of
the simulation. The 2nd fires at 160, the third at
220, etc. This pattern is repeated until the end
of simulation (EOS)
ESIEE, Slide 56
Copyright © 2003 Texas Instruments. All rights reserved.