Lect 5: Protected-Mode Software Architecture

1

Protected-Mode Register Model

EIP EFLAGS GDTR IDTR LDTR CR 0 CR 1 CR 2 CR 3 47 TR Base Base CS DS SS ES FS GS AX BX CX DX SP BP SI DI 16 15 Limit Limit 0 MSW • • • • • • • • • GDTR : global descriptor table LDTR : local descriptor table IDTR : interrupt descriptor table TR : task register EIP : 32 bits in length EFLAGS CR 0 , CR 1 , CR 2 , CR 3 DR 0 -DR 7 (Debug registers) TR 6 -TR 7 (Test registers) DR 0 DR 1 DR 2 DR 3 DR 4 DR 5 DR 6 DR 7 TR 6 TR 7 Maeng Lect05-2

Segment Descriptors

• Descriptor: – the element by which the on-chip memory manager hardware manages the segmentation of the 80386DX’s 64T-byte virtual memory address space.

– One descriptor exists for each segment of memory in virtual address space.

– 8 bytes long and contains three kinds of information • Limit • • Base Access Rights – Types of segment descriptors • system segment descriptor(s=0), non-system segment descriptor(s=1)(code and data) Maeng Lect05-3

Segment Descriptors

3 7 32 24 23 16 15 8 7 BASE 31..24

G X 0 LIMIT 19..16

P DPL S TYPE A BASE 23..16

0 4 SEGMENT BASE 15 .. 0 SEGMENT LIMIT 15 .. 0 0 Maeng Lect05-4

Global Descriptor Table

• Global Descriptor Table – GDT provides a mechanism for defining the characteristics of the 386 global memory address space. Global memory is a general system resource that is shared by many or all software tasks.

– contains system segment descriptors 47 Global Descriptor Table Register(GDTR) 16 15 0 BASE LIMIT 8191 Global Descriptor Table (GDT) MAX: 64k bytes 8K entries 1 0 Maeng Lect05-5

Interrupt Descriptor Table

• Interrupt Descriptor Table (IDT) – – contains interrupt descriptors, not segment descriptors IDT can also be up to 64KB; But 386 only supports up to 256 interrupts and exceptions(2KB) 47 Interrupt Descriptor Table Register(IDTR) 16 15 0 BASE LIMIT 255 Interrupt Descriptor Table (IDT) MAX: 2k bytes 256 entries 1 0 Maeng Lect05-6

Local Descriptor Table

• Local Descriptor Table – Each task can have access to own private descriptor table(LDT) in addition to GDT.

– contains descriptors that provide access to code and data in segments of memory GDTR 31 15 LIMIT 0 BASE   

GDT

LDTR 15 selector 0 LDTR cache 31 15 LIMIT 0 BASE program invisible   

LDT 0

  

LDT n

Maeng Lect05-7

Control Registers

31 23 Page Directory Base Register 15 Page Fault Linear Address 7 P G RESERVED RESERVED 0 CR3 CR2 CR1 R T E M S M P P E CR0 MP: math present EM: emulate R: extension type TS: task switched • MSW : CR0 – the lower 5 bits of CR0 are system-control flags – PE: protected-mode enable bit • At reset, PE is cleared.(real mode) • • Set PE to 1 to enter protected mode Once in protected mode, 386 cannot be switched back to real mode under SW control Maeng Lect05-8

Control Registers and Task Register

• • Paging mechanism – MSB of CR0, CR2, CR3 Task Register – – task switching mechanism TSS descriptor – TSS : task state segment; information needed to initiate the task, such as initial values for the user-accessible registers Physical Memory 47 TR BASE 16 15 LIMIT 0 TSS descriptor TSS GDT Maeng Lect05-9

Register With Changed Functionality

SEGMENT SELECTOR REGISTER

INDEX T I RPL 1-0 Requested Privilege Level(RPL) Indicates selector privilege level desired 2 Table Indicator (TI) TI=0 use global descriptor table (GDT) TI=1 use local descriptor table (LDT) 15-3 Index select descriptor entry in table – Example: CS: 1007H, GDT base 00100000H, LDT base 00120000H • (CS) = 0001 0000 0000 0111 : RPL = 3, TI =1, Index = 0001 0000 0000 0 • Address of the segment descriptor = 00120000H + 1000H = 00121000H Maeng Lect05-10

EFLAGS

31 15 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V R 0 N IO O D I T S Z 0 A 0 P 1 C M F T PL F F F F F F F F F – – – – VM : virtual 8086 Mode - system flag • set only in Protected Mode by IRET instruction and by task switches • unaffected by POPF RF : resume flag - system flag • in conjunction with the debug register breakpoints NT: nested task flag - system flag • indicates that the execution of this task is nested within another task IOPL : input/output privilege flag - system flag • indicates the numerically maximum CPL value permitted to execute I/O instructions Maeng Lect05-11

Protected Memory Management and Address Translation

• Virtual Address and Virtual Address Space – virtual address : selector(16-bit): offset(32-bit) 0 47 selector 32 31 offset INDEX T I RPL – – 2 14 (16,384 = 16K) unique segments of memory, each of which has a maximum size of 4G bytes Total virtual address space = 2 46 , 64 TB Maeng Lect05-12

Protected Memory Management and Address Translation

• Segment Partitioning of the Virtual Address Space Local segment 8191 Local address space 32 Terabytes Local segment 1 Local segment 0 Global segment 8191 Virtual Address Space 64 Terabytes Global address space 32 Terabytes Global segment 1 Global segment 0 Maeng Lect05-13

– Application Program : a collection of tasks • task: a group of program routines that together perform a specific function • A task can activate both global and local segments of memory Task 1 Local Address Space Task 1 Virtual Address Space Task 3 Virtual Address Space Task 3 Local Address Space Global Address Space Task 2 Virtual Address Space Task 2 Local Address Space Maeng Lect05-14

Physical Address Space and Virtual-to Physical Address Translation

SELECTOR LOGICAL ADDRESS OFFSET SEGMENT TRANSLATION PAGING DISABLED LINEAR ADDRESS PG?

PAGING ENABLED 31 DIR PAGE OFFSET 0 PAGE TRANSLATION PHYSICAL ADDRESS Maeng Lect05-15

Segmentation Virtual to Physical Address Translation

SELECTOR LOGICAL ADDRESS OFFSET SEGMENT TRANSLATION PAGING DISABLED PG?

PAGING ENABLED 31 LINEAR ADDRESS DIR PAGE OFFSET 0 Selector Offset(EBX) (DS) PAGE TRANSLATION Data Segment Descriptor Cache Register PHYSICAL ADDRESS Operand Data Segment Segment Descriptor LDT Maeng Lect05-16

Segment Selector Register and the Cache Registers

CS DS SS ES FS GS Programmer accessible Selectors Access Rights Transparently Loaded by MPU Base Address Limit 63 52 51 20 19 0 64-bit Segment Descriptor Cache Registers Maeng Lect05-17