Transcript 5. Programmable Logic Devices

Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
6. Programmable Logic Device
- Programmable Array Logic (PAL)
- Generic Array Logic (GAL)
Tocci Chapter 11 (Memory Devices)
Read section 11-10
Review questions of section 11-10
Chapter 12 (Applications of a PLD)
Read section 12-1 to 12-3
PAL & GAL 1 / page 1
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Programmable Logic Device
 What is a Programmable Logic Device (PLD)?
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an IC that contains large numbers of gates, flip-flops and registers
that are interconnected on the chip
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can be configured by the user to perform a logic function

many of the connections are fusible links that can be broken
PAL & GAL 1 / page 2
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Programmable Logic Device
 Problems of using standard ICs in logic design:
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require hundreds or thousands of these ICs
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require a considerable amount of circuit board space
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require a great deal of time and cost in inserting, soldering,
and testing
require to keep a significant inventory of ICs
PAL & GAL 1 / page 3
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Advantages of using PLDs
 Advantages of reducing the no. of ICs using PLD:
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less board space
fewer printed circuit boards
smaller enclosures
lower power requirements (i.e., smaller power supplies)
faster and less costly assembly processes
higher reliability (fewer ICs and circuit connections => easier
troubleshooting)
availability of design software
PAL & GAL 1 / page 4
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Programmable Logic Device
 Basic Ideas of PLD
 A PLD consists of an array of AND gates and an array of OR gates
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Each input feeds both a non-inverting buffer and an inverting buffer to
produce the true and inverted forms of each variable. (i.e. the input lines
to the AND-gate array)
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The AND outputs are called the product lines
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Each product line is connected to one of the inputs of each OR gate
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Three fundamental types of standard PLDs: PROM, PAL, and PLA
PAL & GAL 1 / page 5
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Internal Structures of PLD
A
B
2-to-4 decoder
A
A
B
B
AND array
AB
AB
AB
AB
AB
AB
AB
AB
Fuse
Input lines
Product
lines
If blown, OR
input is logic 0.
OR
array
O1
O2
O3
O4
Sum of product outputs
Example of a programmable logic device
PAL & GAL 1 / page 6
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Programmable Array Logic (PAL)
D
C
B
A
OR array
(hard-wired)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AND array
(programmable)
O1
O2
O3
O4
PAL & GAL 1 / page 7
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
PAL
 Programmable Array Logic (PAL)

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The input lines to the AND array are programmable and the
output lines to the OR array are hard-wired
Simplify the logic function (e.g. using K-map) before putting
design into PLA.
K-maps
PAL & GAL 1 / page 8
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
PAL
D
E&T1350 Electronics
C
B
A
AND array
(programmable)
OR array
(hard-wired)
0
AB
1
CD
2
0
3
ABC
4
0
5
0
6
0
7
ABCD
8
ABCD
9
0
10
0
11
A
12
BD
13
CD
14
0
15
0
O1
O2 O3
O4
PAL & GAL 1 / page 9
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Programmable Logic Devices
Input lines
Output lines
Versatility
Difficulty in
manufacturing,
programming and
testing
PROM
hard-wired
prog.
low
low
PAL
prog.
hard-wired
moderate
moderate
PLA
prog.
prog.
high
high
PAL & GAL 1 / page 10
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Generic Array Logic (GAL)
 Instead of using one-time programmable fuse links, GAL use an
EEPROM array.
 Block diagram of GAL 16V8A
See Fig. 12-1, P.775, Tocci
 8 dedicated input pins
 2 special function pins (CK, OE)
 8 pins that can be used as inputs or outputs
PAL & GAL 1 / page 11
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Output Structure in PLD

Output logic marcrocells of 16V8R
PAL & GAL 1 / page 12
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Output Structure in PLD
 The macrocell can be individually configured to bypass the
flip-flop.
 The output can either be programmed to be registered (with
flip-flop) or combinational (flip-flop bypassed).
 The PLD can be programmed as sequential or combinational
logic.
PAL & GAL 1 / page 13
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Practical Design of using PLD
 Simple combinational logic implementation
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Example 12-1 and Fig. 12-6, P.780, Tocci
 Simple sequential logic implementation
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Example 12-2 and Fig. 12-8, P.782-3, Tocci
PAL & GAL 1 / page 14
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Programming PLD
 Equipment to design and build circuits using PLDs (Fig. 12-11, P.787)
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personal computer
PLD development software
programming fixture
software to drive the programming fixture
PLD
 JEDEC - a standard format for transferring programming data
for PLDs (independent of PLD manufacturers or software)
PAL & GAL 1 / page 15
Hong Kong Institute of Vocational Education (Tsing Yi)
Electrical and Telecommunications Course Board
E&T1350 Electronics
Development Software
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Allow users to enter their design in some convenient way
Automatically create a JEDEC file
Original software - PALASM (PAL assembler)
Powerful development software tools are referred as compiler. They can
accept more abstract representation of same design and translate it into
hardware details necessary to program the PLD.
e.g. CUPL, ABEL
 Some high-level compiler include schematic capture option allowing entry
operation by drawing a logic circuit diagram
 Logic compiler also allow to enter the design in the form of truth table or state
table. Some even accept timing diagram as input.
PAL & GAL 1 / page 16