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© 2006 IBM Corporation

IBM Research

Multi-Core Design Automation Challenges

John Darringer

IBM T. J. Watson Research Center Yorktown Heights, NY, USA

DAC 2007

© 2007 IBM Corporation

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System Performance Requires An Integrated Approach

200 Device Performance Application Languages, Software Tuning Efficient Programming Middleware Recent Historical Trend System Level 100 Dynamic optimization Assist Threads Fast Computation Power Optimization Compiler Support Production Date 20 1998 2000 2002 2004 2006 2008

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Scaling no longer provides traditional performance boost

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Power limits everything

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Advances will come from entire performance stack Chip Level Technology Compiler Support Multiple Cores SMT Accelerators Power Management Interconnect Circuits Packaging, Cooling New Devices Dense SRAM, eDRAM Optics

Innovation in System Design

3 FPU IDU IFU BXU ISU LSU L2 L2 LSU ISU FPU IFU BXU IDU L2 Power 5

Multi-Thread-2004

Power 4

Multi-Core-2001

Power 6

4.7 Ghz-2007

CELL

Accelerators-2006 © 2006 IBM Corporation

Trend to Modular Application Optimized Systems

SMP Core Cache Accelerator Memory ...

4 Blades

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Growing use of diverse modular components

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Chip integration may evolve to component assembly

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Challenge is in system-level design

– Optimizing architecture for specific applications © 2006 IBM Corporation

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Multi-Core ASICs

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Multi-core ASIC SoCs are common today

– Address broad range of markets – Enables high functional integration – Provides rapid time to market 

One example from 2004

– Cisco Silicon Packet Processor – 188 32-bit RISC processors – 47 BIPS © 2006 IBM Corporation

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Multi-Core Processors

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Power efficient, reusable cores

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Application matched accelerators

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Flexible scaleable interconnect

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Optimized memory hierarchy

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High speed I/O

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Energy management

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Deliver system performance

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Rapid chip assembly to serve diverse markets

© 2006 IBM Corporation

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CHALLENGE

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System Design

– Continued performance growth – Increasing power efficiency – Optimizing for new applications 

Design Automation

– Custom design efficiency – AISC productivity – Design and verification 

Enablers

– Physical Architecture – Integrated Early Analysis – Multi-Core Verification © 2006 IBM Corporation

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Physical Architecture

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Complement logical architecture

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Streamline chip integration

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Plan for interconnect

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Provide predictable results

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Multiple strategies

– Fixed layout per block – Parametric or generated – Extended synthesis

Example Logical Architecture Example Physical Architecture

© 2006 IBM Corporation

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Modular Components

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Components need self-contained vertical stack

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with clean interfaces to enable automated integration Current “Component” Mixed Fabric and Component Function; Custom Interface Current Chips Custom crafting of clock, data, and power meshes Component Fabric Component Function Future Component Future Chips Automated connection with parametric fabric

© 2006 IBM Corporation

Custom Design

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Careful interconnect design

– Communication – Clock distribution – Power and ground 

Better power efficiency

– Clock gating, Power gating – Detailed transistor sizing 

High bandwidth memory and I/O

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Higher frequency operation 10

© 2006 IBM Corporation

Challenges of Modular Design

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Custom Layout

– Flexible shape and orientation – Optimum mesh for power and clock – Distributed communication and test – Manually optimized 

Modular Layout

– Constrained shape and orientation – Separate power and clock per core – Parametric interconnect fabric – Automatic connection to fabric

11 Core Core Core Core Core Core Core Core

© 2006 IBM Corporation

Custom Clock Design

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Distribution network

– Latches and clocked gates – Control skew and jitter – Minimize power – Survive variation and noise 

Interconnect models

– Inductance critical – Transmission line – Buffer placement 

Hand optimized

– Still an art

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Phillip Restle © 2006 IBM Corporation

Custom Power Distribution

        

Distribute to all devices Multiple voltage domains Simulate detailed power demand Model chip and package Consider ground coupling Balance mesh and trees Allocate decoupling capacitors Focus on resonant frequency Explore clock/power gating scenarios 13

Howard Chen © 2006 IBM Corporation

Challenges of Modular Design

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Custom Wiring

– Optimized over chip – Resources shared – Variation minimized – Complex analysis and integration 

Modular Wiring

– Optimized at block level – Fixed resource allocation – Some variation in results – Requires automated integration

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© 2006 IBM Corporation

Spectrum of Strategies

15 Modular Reuse Extended Synthesis Fixed physical architecture

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Fixed Layout …. Parametric Careful block design Custom within block Automated block connect Predictable results Good for planned cases Stresses design ….. Generated Generated physical architecture

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More abstract layout

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Heavy physical synthesis

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Unique block configuration

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Results will vary

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Flexible restructuring

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Stresses tools

© 2006 IBM Corporation

Systems Demand Early Analysis

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To explore many more options

– Cores, Accelerators, Interconnect, Memory Hierarchy, … 

To consider many design criteria simultaneously

– Power, Performance, Latency, Hotspots, Reliability, … 

To optimize system for specific market

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Environment exists for early functional modeling

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But today’s tools are not linked to physical design

© 2006 IBM Corporation

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Early System Analysis

Design Performance Models Assumptions Design Team Technology Power Analysis Implementation Interconnect Analysis Floorplan Thermal Analysis Package

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Loosely coupled disciplines with multiple experts and distinct models

© 2006 IBM Corporation

Performance Modeling Is Changing

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New parallel workloads emerging

– Execution vs. trace driven 

Shifting to multi-core designs

– Stresses balance of model performance and accuracy 

Complex interconnect fabric and memory hierarchy

– Bus, switch, network, asynchronous,… 

Increasing use of SystemC

– For early software development and component sharing © 2006 IBM Corporation

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Early Physical Planning is Essential

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Interconnect requires full chip layout

– Estimate component area before implementation – Need more accurate methods – Have to plan for all facilities to predict chip size 

Placement coupled to many factors

– Interconnect performance – Power – Thermal and reliability concerns – Yield © 2006 IBM Corporation

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Modeling Interconnects in Multi-Core Designs

 Interconnect delays – Effect performance – Depend on placement – Require accurate modeling Core

Cache

Core

Cache

Interconnect Delays

Interconnect Fabric Cache

Core

Cache

Core

Memory Controller

Async/Sync Interface with Parametric delay © 2006 IBM Corporation

Power is Key Criteria, but Hard to Predict

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Need estimate before implementation

– Voltage/Frequency scaling, Voltage islands, clock gating, leakage 

Not just core, but many diverse chip components

– Core, cache, interconnect, controllers, I/O, pervasive 

Model “interesting” states and transitions

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Scale known implementations

– Complex measurement process for calibration – Requires data from chip layout © 2006 IBM Corporation

Integrated Early System Analysis

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Couple all forms of early analysis

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Share data in central repository

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Industry standard data model

– Open Access 

Hand-off to chip integration

– Assumptions, blocks, layout, … 

Graphic interface for editing

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Stage is set for optimization

Design Team

Design Floorplan Package Technology Assumptions Results Handoff

Implementation

22 Performance Power Interconnect Thermal Optimize

© 2006 IBM Corporation

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Multi-Core Verification

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Verification has always been the greatest challenge

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Complexity grows with each generation

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Challenge is to exploit reuse with multi-core designs

– Requires clear interface definition

Core Traditional Approach Core Verification Core Core Core Core Multi-Core Approach System Verification

© 2006 IBM Corporation

Core Verification

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Complexity growing

– Clock/Power gating, Voltage and frequency scaling 

Formal methods are used

– – – Checking RTL = netlist Checking assertions Proving implementation equivalent to reference model 

Simulation still dominates

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Need higher level of specification

– – Improve quality Stretch synthesis and verification tools 

Reuse verification environment

© 2006 IBM Corporation

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System Verification

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More complex systems

– Many cores, accelerators, networks, asynchronous links 

Memory and network contention is critical area

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Formal methods have made impact

– Verifying abstract memory protocols 

Simulation is still the final check

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Need system-level test case generation

– Use system knowledge to expose resource contention issues © 2006 IBM Corporation

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Summary

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Exciting and challenging times

– Designing application optimized multi-core systems – Delivering custom efficiency with ASIC productivity 

Focus areas

– Physical Architecture to streamline chip integration – Integrated Early Analysis to explore design space – Multi-core verification that exploits reuse 

Long history of invention in today’s RTL flow

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Innovation is needed now at the system level

© 2006 IBM Corporation

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Acknowledgements

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Thanks to the following people

– Emrah Acar, Reinaldo Bergamaschi, Pradip Bose, Howard Chen, Nagu Dhanwada, Steven German, Steve Kosonocky, Indira Nair, Ruchir Puri, Phillip Restle, Albert Ruehli, Michael Vinov. © 2006 IBM Corporation

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