Transcript Lecture 3 - Computer Science

COMP541
Multicycle MIPS
Montek Singh
Mar 25, 2010
1
Topics
 Issue w/ single cycle
 Multicycle MIPS
 State elements
 Now add registers between stages
 How to control
 Performance
2
Multicycle MIPS Processor
 Single-cycle microarchitecture:
+ simple
- cycle time limited by longest instruction (lw)
- two adders/ALUs and two memories
 Multicycle microarchitecture:
+ higher clock speed
+ simpler instructions run faster
+ reuse expensive hardware on multiple cycles
- sequencing overhead paid many times
 Same design steps: datapath & control
Multicycle State Elements
 Replace Instruction and Data memories with a single
unified memory
 More realistic
CLK
CLK
PC'
PC
EN
A
CLK
WE
RD
Instr / Data
Memory
A1
A2
A3
WD
WD3
WE3
RD1
RD2
Register
File
Multicycle Datapath: instruction fetch
 First consider executing lw
 STEP 1: Fetch instruction
IRWrite
CLK
CLK
CLK
CLK
WE
PC'
b
PC
A
Instr
RD
Instr / Data
Memory
EN
A1
A2
A3
WD
WD3
WE3
RD1
RD2
Register
File
Multicycle Datapath: lw register read
IRWrite
CLK
CLK
WE
PC'
b
PC
A
Instr
RD
Instr / Data
Memory
EN
CLK
CLK
CLK
25:21
A1
A2
A3
WD
WD3
WE3
RD1
RD2
Register
File
A
Multicycle Datapath: lw immediate
IRWrite
CLK
CLK
WE
PC'
b
PC
A
Instr
RD
CLK
CLK
CLK
25:21
A1
A2
EN
Instr / Data
Memory
A3
WD
WD3
WE3
RD1
A
RD2
Register
File
SignImm
15:0
Sign Extend
Multicycle Datapath: lw address
IRWrite
WE
PC'
b
PC
A
Instr
RD
CLK
CLK
CLK
25:21
A1
A2
EN
WE3
RD1
A
RD2
SrcB
Instr / Data
Memory
A3
WD
WD3
Register
File
SignImm
15:0
Sign Extend
CLK
SrcA
ALU
CLK
CLK
ALUControl2:0
ALUResult
ALUOut
Multicycle Datapath: lw memory read
IRWrite
CLK
CLK
ALUControl2:0
WE
PC'
b
PC
0
1
Adr
A
Instr / Data
Memory
WD
Instr
RD
CLK
CLK
CLK
25:21
A1
A2
EN
WE3
RD1
A
RD2
SrcB
A3
CLK
Data
WD3
Register
File
SignImm
15:0
Sign Extend
CLK
SrcA
ALU
IorD
ALUResult
ALUOut
Multicycle Datapath: lw write register
IRWrite
CLK
CLK
RegWrite
WE
PC'
b
PC
0
1
Adr
A
Instr / Data
Memory
WD
Instr
RD
CLK
CLK
CLK
25:21
A1
A2
EN
ALUControl2:0
WE3
RD1
A
RD2
SrcB
20:16
CLK
Data
A3
WD3
Register
File
SignImm
15:0
Sign Extend
CLK
SrcA
ALU
IorD
ALUResult
ALUOut
Multicycle Datapath: increment PC
Now using main ALU when it’s not busy
IorD
IRWrite
CLK
CLK
RegWrite
WE
PC'
b
EN
PC
0
1
Adr
A
Instr / Data
Memory
WD
Instr
RD
CLK
CLK
CLK
25:21
A1
A2
EN
ALUSrcA ALUSrcB1:0 ALUControl2:0
WE3
0
RD1
A
RD2
00
4
20:16
CLK
Data
A3
WD3
Sign Extend
01
10
Register
File
11
SignImm
15:0
SrcA
1
SrcB
CLK
ALU
PCWrite
ALUResult
ALUOut
Multicycle Datapath: sw
 Already know how to generate addr
 Write data in rt to memory
IorD
MemWrite IRWrite
CLK
CLK
RegWrite
WE
PC'
b
EN
PC
0
1
Adr
A
Instr / Data
Memory
WD
Instr
RD
CLK
CLK
CLK
25:21
20:16
EN
A1
A2
ALUSrcA ALUSrcB1:0 ALUControl2:0
WE3
0
RD1
RD2
A
B
00
4
20:16
CLK
Data
A3
WD3
Register
File
Sign Extend
01
10
11
SignImm
15:0
SrcA
1
SrcB
CLK
ALU
PCWrite
ALUResult
ALUOut
Multicycle Datapath: R-type Instrs.
 Read from rs and rt
 Write ALUResult to register file
 Write to rd (instead of rt)
IorD
MemWrite IRWrite
CLK
CLK
RegDst MemtoReg
b
EN
PC
0
1
Adr
A
Instr
RD
A1
20:16
EN
Instr / Data
Memory
WD
25:21
20:16
15:11
CLK
A2
WE3
0
RD1
RD2
A
0
A3
1
1
WD3
B
00
Register
File
Sign Extend
01
10
11
SignImm
15:0
SrcA
1
4
0
Data
ALUSrcA ALUSrcB1:0 ALUControl2:0
CLK
CLK
CLK
WE
PC'
RegWrite
SrcB
CLK
ALU
PCWrite
ALUResult
ALUOut
Multicycle Datapath: beq
•
•
Determine whether values in rs and rt are equal
Calculate branch target address:
BTA = (sign-extended immediate << 2) + (PC+4)
ALU reused
•
PCEn
MemWrite IRWrite
CLK
CLK
PC'
b
EN
PC
1
Adr
A
Instr
RD
EN
Instr / Data
Memory
WD
RegWrite
CLK
25:21
A1
20:16
A2
20:16
0
15:11
1
WE3
0
RD1
RD2
A
A3
1
WD3
B
00
11
SignImm
Sign Extend
01
10
Register
File
<<2
15:0
SrcA
1
4
0
Data
ALUSrcA ALUSrcB1:0 ALUControl2:0 Branch PCWrite
PCSrc
CLK
CLK
CLK
WE
0
RegDst MemtoReg
SrcB
Zero
ALU
IorD
CLK
0
ALUResult
ALUOut
1
Complete Multicycle Processor
CLK
PCWrite
PCEn
Branch
IorD Control PCSrc
ALUControl2:0
Unit
MemWrite
ALUSrcB1:0
IRWrite
5:0
PC
EN
0
1
Adr
A
Instr
RD
25:21
20:16
EN
Instr / Data
Memory
WD
MemtoReg
CLK
WE
PC'
RegWrite
Funct
RegDst
CLK
CLK
ALUSrcA
Op
20:16
15:11
CLK
A1
A2
WE3
0
RD1
RD2
A
0
A3
1
1
WD3
B
00
Register
File
11
SignImm
Sign Extend
01
10
<<2
15:0
SrcA
1
4
0
Data
CLK
CLK
SrcB
Zero
ALU
31:26
CLK
0
ALUResult
ALUOut
1
Control Unit
Control
Unit
Opcode5:0
MemtoReg
RegDst
IorD
Main
Controller
(FSM)
PCSrc
ALUSrcB1:0
ALUSrcA
IRWrite
MemWrite
PCWrite
Branch
RegWrite
ALUOp1:0
Funct5:0
ALU
Decoder
ALUControl2:0
Multiplexer
Selects
Register
Enables
Main Controller FSM: Fetch
S0: Fetch
Reset
CLK
1
PCWrite
0
Branch
PCEn
IorD Control PCSrc
ALUControl2:0
Unit
MemWrite
ALUSrcB1:0
IRWrite
5:0
PC
EN
1
0
1
CLK
WE
Adr
A
Instr / Data
Memory
WD
Instr
RD
MemtoReg
0
PC'
0
RegWrite
Funct
RegDst
CLK
CLK
ALUSrcA
Op
25:21
20:16
EN
CLK
20:16
0
15:11
1
WE3
0
CLK
0
0
RD1
RD2
A
A3
X
1
WD3
B
01
10
Register
File
11
SignImm
Sign Extend
01
00
<<2
15:0
SrcA
1
4
0
Data
A1
A2
X
1
CLK
SrcB
010
ALU
31:26
Zero
CLK
0
0
ALUResult
ALUOut
1
Main Controller FSM: Fetch
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
• Fetch instruction
• Also increment PC (because ALU not in use)
CLK
1
PCWrite
0
Branch
31:26
5:0
0
PC'
PC
EN
1
0
1
0
CLK
WE
Adr
A
Instr / Data
Memory
WD
Instr
RD
RegWrite
Funct
MemtoReg
CLK
CLK
ALUSrcA
Op
RegDst
Note: signals
only shown
when needed
and enables
only when
asserted.
PCEn
IorD Control PCSrc
ALUControl2:0
Unit
MemWrite
ALUSrcB1:0
IRWrite
25:21
20:16
EN
1
CLK
0
15:11
1
WE3
0
CLK
0
0
RD1
RD2
A
A3
X
1
WD3
B
01
10
Register
File
11
SignImm
Sign Extend
01
00
<<2
15:0
SrcA
1
4
0
Data
A1
A2
X
20:16
CLK
SrcB
010
ALU
Reset
Zero
CLK
0
0
ALUResult
ALUOut
1
Main Controller FSM: Decode
Reset
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
S1: Decode
• No signals needed for decode
• Register values also fetched
• Perhaps will not be used
CLK
0
PCWrite
0
Branch
PCEn
IorD Control PCSrc
ALUControl2:0
Unit
MemWrite
ALUSrcB1:0
IRWrite
31:26
5:0
PC
EN
0
0
1
CLK
WE
Adr
A
Instr / Data
Memory
WD
Instr
RD
MemtoReg
X
PC'
0
RegWrite
Funct
RegDst
CLK
CLK
ALUSrcA
Op
25:21
20:16
EN
0
CLK
0
15:11
1
WE3
X
CLK
0
0
RD1
RD2
A
A3
X
1
WD3
B
01
10
Register
File
11
SignImm
Sign Extend
XX
00
<<2
15:0
SrcA
1
4
0
Data
A1
A2
X
20:16
CLK
SrcB
XXX
Zero
ALU
S0: Fetch
CLK
X
0
ALUResult
ALUOut
1
Main Controller FSM:
Reset
S2: MemAdr
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
S1: Decode
• Now change states depending on instr
Op = LW
or
Op = SW
CLK
0
PCWrite
0
Branch
PCEn
IorD Control PCSrc
ALUControl2:0
Unit
MemWrite
ALUSrcB1:0
IRWrite
31:26
5:0
PC
EN
0
0
1
CLK
WE
Adr
A
Instr / Data
Memory
WD
Instr
RD
MemtoReg
X
PC'
0
RegWrite
Funct
RegDst
CLK
CLK
ALUSrcA
Op
25:21
20:16
EN
CLK
20:16
0
15:11
1
WE3
1
CLK
0
0
RD1
RD2
A
A3
X
1
WD3
B
01
10
Register
File
11
SignImm
Sign Extend
10
00
<<2
15:0
SrcA
1
4
0
Data
A1
A2
X
0
CLK
SrcB
010
ALU
S0: Fetch
Address Calculation
Zero
CLK
X
0
ALUResult
ALUOut
1
Main Controller FSM:
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S2: MemAdr
Address Calculation
S1: Decode
• For lw or sw, need to compute addr
Op = LW
or
Op = SW
CLK
0
PCWrite
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
0
Branch
PCEn
IorD Control PCSrc
ALUControl2:0
Unit
MemWrite
ALUSrcB1:0
IRWrite
5:0
PC
EN
0
0
1
CLK
WE
Adr
A
Instr / Data
Memory
WD
Instr
RD
MemtoReg
X
PC'
0
RegWrite
Funct
RegDst
CLK
CLK
ALUSrcA
Op
25:21
20:16
EN
CLK
20:16
0
15:11
1
WE3
1
CLK
0
0
RD1
RD2
A
A3
X
1
WD3
B
01
10
Register
File
11
SignImm
Sign Extend
10
00
<<2
15:0
SrcA
1
4
0
Data
A1
A2
X
0
CLK
SrcB
010
ALU
31:26
Zero
CLK
X
0
ALUResult
ALUOut
1
Main Controller FSM: lw
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S2: MemAdr
Op = LW
or
Op = SW
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
Op = LW
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
S1: Decode
• For lw now
need to read
from memory
• Then write to
register
Main Controller FSM: sw
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S2: MemAdr
S1: Decode
Op = LW
or
Op = SW
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
Op = SW
Op = LW
S5: MemWrite
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
IorD = 1
MemWrite
• sw just writes
to memory
• One step
shorter
Main Controller FSM: R-Type
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S2: MemAdr
S1: Decode
Op = LW
or
Op = SW
Op = R-type
S6: Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
Op = SW
Op = LW
S5: MemWrite
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
IorD = 1
MemWrite
S7: ALU
Writeback
RegDst = 1
MemtoReg = 0
RegWrite
• The r-type
instructions
have two steps:
compute result
in ALU and
write to reg
Main Controller FSM: beq
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S2: MemAdr
S1: Decode
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Op = BEQ
Op = LW
or
Op = SW
Op = R-type
S6: Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
S8: Branch
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 1
Branch
beq needs to
use ALU twice,
so consumes
two cycles
• One to
compute addr
•Another to
decide on eq
Op = SW
Op = LW
S5: MemWrite
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
IorD = 1
MemWrite
S7: ALU
Writeback
RegDst = 1
MemtoReg = 0
RegWrite
Can take
advantage of
decode when
ALU not used to
compute BTA
(no harm if BTA
not used)
Complete Multicycle Controller FSM
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S2: MemAdr
S1: Decode
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Op = BEQ
Op = LW
or
Op = SW
Op = R-type
S6: Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
Op = SW
Op = LW
S5: MemWrite
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
IorD = 1
MemWrite
S7: ALU
Writeback
RegDst = 1
MemtoReg = 0
RegWrite
S8: Branch
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 1
Branch
Main Controller FSM: addi
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S2: MemAdr
Similar to r-type
S1: Decode
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Op = BEQ
Op = LW
or
Op = SW
Op = ADDI
Op = R-type
S6: Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
S8: Branch
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 1
Branch
S9: ADDI
Execute
Op = SW
Op = LW
S5: MemWrite
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
IorD = 1
MemWrite
S7: ALU
Writeback
RegDst = 1
MemtoReg = 0
RegWrite
S10: ADDI
Writeback
• Add
• Write back
Main Controller FSM: addi
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S2: MemAdr
S1: Decode
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Op = BEQ
Op = LW
or
Op = SW
Op = ADDI
Op = R-type
S6: Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
S8: Branch
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 1
Branch
S9: ADDI
Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
Op = SW
Op = LW
S5: MemWrite
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
IorD = 1
MemWrite
S7: ALU
Writeback
RegDst = 1
MemtoReg = 0
RegWrite
S10: ADDI
Writeback
RegDst = 0
MemtoReg = 0
RegWrite
Extended Functionality: j
PCEn
MemWrite IRWrite
CLK
CLK
RegDst MemtoReg
PC
EN
0
1
Adr
A
Instr
RD
EN
Instr / Data
Memory
WD
25:21
A1
20:16
A2
20:16
15:11
CLK
WE3
RD1
RD2
A
0
31:28
A3
1
0
1
WD3
B
00
Register
File
11
SignImm
25:0 (jump)
Sign Extend
01
10
<<2
15:0
SrcA
1
4
0
Data
ALUSrcA ALUSrcB1:0 ALUControl2:0 Branch PCWrite
PCSrc1:0
CLK
CLK
CLK
WE
PC'
RegWrite
SrcB
CLK
Zero
ALU
IorD
00
ALUResult
ALUOut
01
10
PCJump
<<2
27:0
Control FSM: j
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 00
IRWrite
PCWrite
Reset
S2: MemAdr
S1: Decode
S11: Jump
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Op = J
Op = BEQ
Op = LW
or
Op = SW
Op = ADDI
Op = R-type
S6: Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
S8: Branch
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 01
Branch
S9: ADDI
Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
Op = SW
Op = LW
S5: MemWrite
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
IorD = 1
MemWrite
S7: ALU
Writeback
RegDst = 1
MemtoReg = 0
RegWrite
S10: ADDI
Writeback
RegDst = 0
MemtoReg = 0
RegWrite
Control FSM: j
S0: Fetch
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 00
IRWrite
PCWrite
Reset
S2: MemAdr
S1: Decode
S11: Jump
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Op = J
PCSrc = 10
PCWrite
Op = BEQ
Op = LW
or
Op = SW
Op = ADDI
Op = R-type
S6: Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
S8: Branch
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 01
Branch
S9: ADDI
Execute
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
Op = SW
Op = LW
S5: MemWrite
S3: MemRead
IorD = 1
S4: Mem
Writeback
RegDst = 0
MemtoReg = 1
RegWrite
IorD = 1
MemWrite
S7: ALU
Writeback
RegDst = 1
MemtoReg = 0
RegWrite
S10: ADDI
Writeback
RegDst = 0
MemtoReg = 0
RegWrite
Multicycle Performance
 Instructions take different number of cycles:
 3 cycles:
beq, j
 4 cycles:
R-Type, sw, addi
 5 cycles: lw
 CPI is weighted average
 SPECINT2000 benchmark:
 25% loads
 10% stores
 11% branches
 2% jumps
 52% R-type
 Average CPI = (0.11 + 0.2)(3) + (0.52 + 0.10)(4) +
(0.25)(5) = 4.12
Multicycle Performance
• Multicycle critical path:
Tc = tpcq + tmux + max(tALU + tmux, tmem) + tsetup
CLK
PCWrite
PCEn
Branch
IorD Control PCSrc
ALUControl2:0
Unit
MemWrite
ALUSrcB1:0
IRWrite
5:0
PC
EN
0
1
Adr
A
Instr
RD
25:21
20:16
EN
Instr / Data
Memory
WD
MemtoReg
CLK
WE
PC'
RegWrite
Funct
RegDst
CLK
CLK
ALUSrcA
Op
CLK
0
15:11
1
WE3
0
RD1
RD2
A
A3
1
WD3
B
00
11
SignImm
Sign Extend
01
10
Register
File
<<2
15:0
SrcA
1
4
0
Data
A1
A2
20:16
CLK
CLK
SrcB
Zero
ALU
31:26
CLK
0
ALUResult
ALUOut
1
Multicycle Performance Example
Element
Parameter
Delay (ps)
Register clock-to-Q tpcq_PC
30
Register setup
tsetup
20
Multiplexer
tmux
25
ALU
tALU
200
Memory read
tmem
250
Register file read
tRFread
150
Register file setup
tRFsetup
20
Tc = tpcq_PC + tmux + max(tALU + tmux, tmem) + tsetup
= tpcq_PC + tmux + tmem + tsetup
= [30 + 25 + 250 + 20] ps
= 325 ps
Multicycle Performance Example
 For a program with 100 billion instructions executing
on a multicycle MIPS processor
 CPI = 4.12

Tc = 325 ps
 Execution Time = (# instructions) × CPI × Tc
= (100 × 109)(4.12)(325 × 10-12)
= 133.9 seconds
 This is slower than the single-cycle processor (92.5 seconds).
Why?
 Not all steps the same length
 Sequencing overhead for each step (tpcq + tsetup= 50 ps)
Review: Single-Cycle MIPS Processor
Jump
31:26
5:0
MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0
Op
ALUSrc
Funct
RegDst
PCSrc
RegWrite
CLK
0
1
0
PC'
PC
1
A
RD
Instr
Instruction
Memory
25:21
20:16
A1
A2
A3
WD3
CLK
WE3
RD2
0 SrcB
1
Register
File
20:16
PCJump
+
WriteReg4:0
PCPlus4
WriteData
1
SignImm
Sign Extend
<<2
+
15:0
ALUResult
0
15:11
4
Zero
SrcA
RD1
ALU
CLK
27:0
31:28
25:0
<<2
PCBranch
WE
A
RD
Data
Memory
WD
ReadData
0 Result
1
Review: Multicycle MIPS Processor
CLK
PCWrite
PCEn
Branch
IorD Control PCSrc
ALUControl2:0
Unit
ALUSrcB1:0
IRWrite
MemWrite
5:0
ALUSrcA
Op
RegWrite
Funct
MemtoReg
RegDst
CLK
CLK
WE
PC'
PC
EN
0
1
Adr
A
Instr
RD
25:21
A1
20:16
EN
Instr / Data
Memory
WD
CLK
CLK
CLK
20:16
15:11
CLK
A2
RD1
RD2
A
0
31:28
A3
1
0
1
WD3
B
00
Register
File
11
ImmExt
25:0 (Addr)
Sign Extend
01
10
<<2
15:0
SrcA
1
4
0
Data
WE3
SrcB
CLK
Zero
ALU
31:26
00
ALUResult
ALUOut
01
10
PCJump
<<2
27:0
Next Time
 We’ll look at pipelined MIPS
 Adding throughput (and complexity) by trying to use
all hardware every cycle
38